搜索资源列表
c
- 求100以内偶数和,动态规划,动态建对象数组,素数,环路-prime,circle
PLL
- 锁相环路的基本工作原理 PLL basic working principal-The basic working principle of PLL PLL basic working principal
matlabsuanfa
- 包含了Floyd算法、dijkstra算法、贪婪算法、遗传算法、搜索算法、蚁群算法、哈密顿环路的matlab源程序及相关说明。-Floyd algorithm is included, dijkstra algorithm, greedy algorithm, genetic algorithm, search algorithm, ant colony algorithm, Hamiltonian loop matlab source code and instructions.
chaoliu
- 【配网潮流计算程序】本程序采用前推回代法,适用于35kV以下辐射型开式网络潮流计算,且若支路有备用支路需换算为单支路再行计算,适用于回路无环路时(有详细程序说明)。-【Distribution network load flow calculation program】 This procedure uses forward and backward on behalf of the law applicable to the following radiation-type open-35kV
myd1loop
- dm642图像采集显示环路实验,在dm642开发平台上运行通过-dm642 image acquisition shows the loop experiment, in the dm642 development platform to run through the
Tcpip_loopback
- dm642 tcp/ip协议开发,数据发收环路,在dm642平台上运行通过-dm642 tcp/ip protocol development, data issued closed-loop, in the dm642 platforms through
lgmFramework
- dm642 tcp/ip协议开发,数据发收环路,在dm642平台上运行通过-dm642 tcp/ip protocol development, data issued closed-loop, in the dm642 platforms through
chargepumppll1
- PLL时域仿真器,用来对PLL环路稳定性进行判断-PLL time domain simulator
QAMtimingrecovery
- QAM的定时恢复资料,对其中的定时环路做了详细的讲解,希望对大家有用。-QAM timing recovery information on the timing loop which made a detailed explanation, hope for all of us.
DVB-TIF
- 本文从应用于数字地面电视广播 DVB-T 接收机中的频率综合器研究为出发点, 首先,简单介绍了DVB-T 接收机对频率综合器的性能要求,概括了频率综合器的 结构和分析方法。在此基础上,着重研究了频率综合器的环路参数设计和噪声估计 方法,并采用TSMC 0.25μm CMOS 工艺设计了一个窄带的频率综合器加以验证。-DVB IF
ModifyInstruction
- 数字环路滤波器是由变模可逆计数器构成的。 该计数器设计为一个17 位可编程(可变模数) 可逆 计数器,计数范围是,由外部置数DCBA 控制-Digital loop filter is composed of variable-mode reversible counter. The counter is designed to a 17-bit programmable (variable modulus) reversible counter, counting range is s
VOIPIP
- 描述了因特网和IP的主要特征,包括包丢失和时延抖动,并让读者了解数字信号处理器(DSP)和语音编码器在VoIP中所扮演的角色。本书还为读者讲述了如何通过ISDN、xDSL、HFC本地环路或其他途径建立与业务提供商之间的通路,以及目前主要的IP电话协议-Describes the main features of the Internet and IP, including packet loss and delay jitter, and to allow readers to understa
bulkext
- ezusb 批量端点间和外部RAM环路测试-ezusb bulkext is FX2 bulk loopback firmware. It loops back EP2OUT-> EP6IN and EP4OUT-> EP8IN The loopback is performed using the external auto pointer. Data is copied from the OUT endpoint buffer to external RA
PLL(lin)
- 一个用MATLAB 实现的锁相环路得程序-a program of phase loop link using the tool of simulink
QPSKdigitalreceiver
- QPSK全数字接收机PDF,详细介绍了QPSK全数字接收机的构成,环路滤波器、内插器、Gardner定时恢复等部分的详细设计-QPSK digital receiver PDF, details of the composition of QPSK digital receiver, loop filter, interpolator, Gardner Timing Recovery and other parts of the detailed design
AGC
- 在实际系统中,由于发端功率和信道增益的变化会引起接收到的信号幅度的变化,这种变化是设计者所不希望的,因此,有必要对信号幅度进行自动增益控制(AGC)。另外,在解调器内部所有同步完成之后,如果解调输出为软输出,则需要对输出信号进行定标,以使较少的位数能够全面地反映解调数据的信息,这被称为定标AGC。AGC的实现原理大同小异,一般都是将信号幅度(能量)与固定门限比较,高于或低于门限的信息被送到调整环路滤波器,滤波器的输出用于控制可控增益放大器,或者是数字增益调整。-AGC
shuangjidian
- 双极点滤波算法,由两个反馈环路组成,通过更改反馈系数得到不一样的系统增益-Pole filter algorithm consists of two feedback loop formed by changing the feedback factor are not the same as the system gain
xx
- 本工程基于CYPRESS的固件程序框架,程序中通过使能端点中断,进行端点间数据的传送;利用端点中断进行环路测试-The project framework based on the firmware CYPRESS, proceedings interrupted by enabling the endpoint, to transmit data between endpoints use of endpoint interrupt loop test
ceshi
- keil编写,本工程基于CYPRESS的固件程序框架,程序中设置了4个FIFO端点,可实现批量端点间和外部RAM环路测试-keil preparation, the project CYPRESS firmware based framework, the program set up four FIFO endpoint, can be realized between the ends and external RAM volume loop testing
dpll
- 本文介绍了锁相环路的基本原理,并着重分析了数字锁相环的结构、原理。利用Verilog语言对数字锁相环的主要模块进行了设计,并用Modelsim软件进行仿真。最后给出了整个系统的仿真结果,验证设计的正确性,并在现场可编程门阵列FPGA上予以实现-dpll