搜索资源列表
big-leds
- 51单片机 + 8位锁存器 + 4线-16线译码器 实现超大静态字体显示,显示字体16*16点阵 * 10。 主函数 10 行代码。-51 mcu, 8 bit latch and four to sixteen decorder. main function just ten lines.
adsawfd
- 用Verilog HDL设计3线-8线译码器,ena是译码器的使能控制端,当ena=1时译码器工作,ena=0时译码器被禁止,8个输出均为高电平 用Verilog HDL设计具有三态输出的8D锁存器。-3-to-8 line decoder, ENA is designed using Verilog HDL the decoder enable control terminal, when ena = 1 time decoder, ENA = 0 time decoder is disa
shumaguan
- STC系列单片机————运用74HC595锁存器 矩形键盘按键在数码管上显示相应数字-The STC MCU---- use 74HC595 latch rectangular keyboard keys digital display corresponding figures
shumaguan
- ICCAVRat48数码管显示基于ch164数据锁存器的单个数码管显示0123456789显示小程序-ICCAVRat48 digital display data latch based ch164 single digital display shows the applet 0123456789
lilei127-01
- 我是新人,很高兴通过朋友介绍得知这个网站。动态显示的特点是将所有位数码管的段选线并联在一起,由位选线控制是哪一位数码管有效。这样一来,就没有必要每一位数码管配一个锁存器,从而大大地简化了硬件电路。选亮数码管采用动态扫描显示。所谓动态扫描显示即轮流向各位数码管送出字形码和相应的位选,利用发光管的余辉和人眼视觉暂留作用,使人的感觉好像各位数码管同时都在显示。动态显示的亮度比静态显示要差一些,所以在选择限流电阻时应略小于静态显示电路中的。 -I was new, I am glad that t
dsw
- P0与J12 用8PIN排线连接, P1与JP16 用排线连接,573锁存器控制和单片机脚直接位选控制(非译码器控制)数码管。-P0 and J12 cable to connect with 8PIN, P1 and JP16 with a ribbon cable, 573 feet latch control and chip select control bits directly (non-decoder control) digital tube.
my_led
- NXP LPC1114驱动LED灯,带锁存器功能。-NXP LPC1114 drive LED lights, with latch function.
dele
- 问片外存储器时,下降沿用于控制外接的地址锁存器锁存从P0口输出的低8位地址。在没有接外部存储器时,可以将该引脚的输出作为时钟信号使用-Q-chip memory, the falling edge is used to control an external address latch P0 port output latch from the lower 8-bit address. In the absence of access to external memory, you can co
ok
- 问片外存储器时,下降沿用于控制外接的地址锁存器锁存从P0口输出的低8位地址。在没有接外部存储器时,可以将该引脚的输出作为时钟信号使用-Q-chip memory, the falling edge is used to control an external address latch P0 port output latch from the lower 8-bit address. In the absence of access to external memory, you can co
fa
- 问片外存储器时,下降沿用于控制外接的地址锁存器锁存从P0口输出的低8位地址。在没有接外部存储器时,可以将该引脚的输出作为时钟信号使用-Q-chip memory, the falling edge is used to control an external address latch P0 port output latch from the lower 8-bit address. In the absence of access to external memory, you can co
delta-sigma-DAC
- 根据FPGA的∑-Δ D/A转换器的设计与实现策略,∑-Δ DAC的内部仅由2个10位的二进制加法器,1个10位的锁存器和一个D触发器组成,用FPGA实现时只需耗费极少的逻辑资源,即使用最小的FPGA也能实现。这是∑-Δ DAC实现的verilog语言-According to the FPGA Σ-Δ D/A converter design and implementation strategies, Σ-Δ DAC' s internal only by the two 10-bit
software_reset
- 单片机通过两个锁存器控制数码管显示,用软件实现复位。-MCU through two latches control the digital display, with software reset.
HEX
- PROTEL仿真电路程序 573锁存器+单个数码管+定时器测试程序
HEX
- PROTEL仿真电路程序 573锁存器+单个数码管+定时器
latch
- FPGA锁存器代码,EPM240上已经验证了,可以借鉴使用,用Verilog语言编写-FPGA latches code, EPM240 has been verified, you can learn to use, with the Verilog language
zwcfq
- 带置位和复位端的1 位数据锁存器,源代码verilo实现,在quartusII平台上,大家试试看。-With set and reset terminal a data latch, the source code verilo achieve, in the quartusII platform, we try.
C
- 用573锁存器控制和单片机脚直接位选控制(非译码器控制)数码管上显示数字-Latches with 573 control and direct bit microcontroller pin select control (non-decoder control) digital display digital
GUANGLIFAN
- 4*4*4光立方,直联方式,不需要锁存器,适合初学-4* 4* 4 Light Cube, Direct mode, no latches
ET6226-DEMO-Board-code
- ET6226 是一种带键盘扫描电路接口的LED 驱动控制专用电路。内部集成有MCU 输入输出控制数字 接口、数据锁存器、LED 驱动、键盘扫描、辉度调节等电路。本芯片性能稳定、质量可靠、抗干扰能力强, 可适应于24 小时长期连续工作的应用场合。-A kind of LED driver for STB.
Latch_sram
- FPGA内部集成RAM和锁存器模块设计,欢迎大家来验证-FPGA internal RAM and latches integrated module design, welcome to verify