4位乘法器,4位除法器 8位数据锁存器,8位相等比较器,带同步复位的状态 机,元件例化与层次设计,最高优先级编码器-four multipliers, dividers four eight data latches, and eight other phase comparators, synchronous reset with the state machine, the component level with the cases of design, the highest

Ｄ锁存器ＶＨＤＬ语言描述。使能端有效时，Ｑ《＝Ｄ-D latch described in VHDL language. Enable effective end when, Q " = D