搜索资源列表
PLL
- 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
simple_pll_3
- 简单的模拟锁相环仿真，基于simulink平台使本地震荡频率跟上接收到得频率-analog pll simulation,based on simulink
pll
- 设计的软件锁相环的例子，自己写的，根据原理编的-PLL design example of software that he wrote, according to the principle for the
pll_verilog
- 全数字锁相环的verilog源代码,仿真已通过 -All-Digital Phase-Locked Loop verilog source code, simulation has passed
PLL
- 用VHDL和matlab编写的数字锁相环电路。-Matlab with VHDL and digital phase-locked loop circuit prepared.
pll
- 摘要:叙述了全数字锁相环的工作原理,提出了应用VHDL 技术设计全数字锁相环的方法,并用复杂可编程逻辑器件CPLD 予以实现,给出了系统主要模块的设计过程和仿真结果。-Abstract: This paper describes the working principle of an all-digital phase-locked loop is proposed application VHDL technical design an all-digital phase-locked loo
PLL
- LM3236锁相环程序设计-LM3236 PLL program design
PrenticeHallPrincipleofCommunicationSystemSmulatio
- 本书分成三部分，第一部分讨论了仿真的作用和方法论。第二部分介绍了采样定理，滤波器模型、锁相环等的仿真。第三部分是高层建模与仿真方法。-The book is divided into three parts, the first section discusses the role of simulation and methodology. The second part of the sampling theorem, the filter model, phase-locked loop
divde_clk10m
- 一种带负反馈,无见相思曲的高精度锁相环,采用双D触发器实现-PLL
PLL(lin)
- 锁相环的设计主要用于载波跟踪代码，在载波跟踪捕获当中可能会用到的源代码-PLL design is mainly used for carrier tracking code, the carrier capture which may be used to track the source code
Cckk6
- 通信系统仿真原理与无线应用第六章的程序，是关于锁相环与微分方程的。-failed to translate
VHDLDPLL
- 基于VHDL 的全数字锁相环的设计，里面包含了最核心的程序。-VHDL-based all-digital phase-locked loop design, which contains the core procedures.
DSP3
- 基于DSP的三相软件锁相环设计基于DSP的三相软件锁相环设计-DSP-Based Design of SPLL
pll-matlab
- 通信常用锁相环仿真－matlab格式－有简单注释。-Communications Common PLL simulation-matlab format- a simple comment.
DPLL
- 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
altpll0
- 锁相环的证实程序，可以在任何编译器中执行，但是要是TI公司的平台。-Confirmed by phase-locked loop process can be run on any compiler, but if TI' s platform。
003
- 只是一个利用MATLAB实现同步数字锁相环仿真程序-Is just a realization of synchronous digital phase-locked loop using MATLAB simulation program
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
DPLL_verilog_a
- 用verilog语言描写设计的全数字锁相环，pDF资料-With the verilog language to describe the design of all-digital phase-locked loop, pDF information
dig_pll
- 一个简易的数字锁相环，可以产生一个与输入同频同相的输出时钟-A simple digital PLL can generate an input in phase with the same frequency output clock