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mypll_qpsk
- MATALAB编写的QPSK用于载波同步的锁相环，其结构为平方环-MATALAB编写的QPSK的用于载波同步的锁相环，其结构为平方环
soniclean200812161411248509
- 这是一篇关于cmos锁相环频率合成器的文章-this is an article of cmos pll
PLL
- 利用锁相环，比较好的实现了载波同步-PLL
PLLC
- 平方载波同步法的MATLAB实现 锁相环部分的仿真程序 结果正确 可以直接使用-PLLC.M
altpllpll
- 用VHDL语言编写的锁相环源代码，可用于配置FPGA，在FPGA中实现ＰＬＬ功能。-VHDL language with PLL source code, can be used to configure the FPGA, PLL function is implemented in the FPGA.
QPSK4_Weitongbu
- 关于定时同步的Matlab仿真代码，采用锁相环技术实现-Matlab code for Timing recovery using PLL
weitongbu
- 数字锁相环实现位同步信号的提取,含电路图，和源代码-Digital phase-locked loop to achieve bit synchronization signal extraction, including schematics, and source code
weitongbu
- 用数字锁相环实现位同步信号提取，包含各个模块的电路设计程序。-To achieve bit synchronization with digital phase-locked loop signal extraction, each module contains the circuit design process.
frerecov
- 通信系统中有关于利用锁相环完成载波跟踪恢复的仿真功能-Communication system using phase-locked loop on the completion of the simulation function to restore the carrier tracking
pll_sim
- 这是一个根据锁相环原理编写的MATLAB仿真程序，内有详细注释，同时附带了仿真结果图。-It is MATLAB simulation program of phase locked loop,while with the simulation results Fig.
Matlabpll
- 基于Matlab的数字锁相环的仿真设计，一篇毕业论文，对数字和模拟锁相环进行了详细的分析和仿真-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
PLLC
- 本程序利用平方环实现载波同步，使用锁相环进行跟踪相位偏移-This program makes use of the square ring to achieve carrier synchronization, with the use of PLL to track the phase shift
DesignoftrackingloopofGPSsoftwarereceiver
- 本文在分析GPS 软件接收机跟踪原理的基础上，首先比较码环与载波环不同鉴相器的性能，然后对二阶锁相环中不同环路参数设下的跟踪效果进行仿真分析，最后设计 了合适的码环与载波环路，并用实际采集的GPS 数据论证了所设计环路的有效性，为GPS 软件接收机跟踪环路的设计提供了参考。-Based on the analysis of GPS receiver tracking software on the basis of the principle, first compare the diffe
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
84f704a6df6c
- 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。-MC145159 PLL frequency synthesizer design and realization of PLL frequency synthesizer the basic principles of integrated PLL chip M C 145159 work characteristic
vhdl3
- 介绍一种基于VHDL 语言的全数字锁相环实现方法， 并用这种方法在FPGA 中实现了全 数字锁相环，作为信号解调的位同步模块。-Introduction of a language based on VHDL implementations of DPLL, and this method is implemented in the FPGA digital phase locked loop, as the signal demodulation of bit synchronizatio
pll
- 用matlab模拟仿真锁相环，一个很好的程序，希望能帮到你-PLL with matlab simulation, a very good program, hope you can help
Phase-locked-loop
- 该程序是锁相环的MATLAB的简单实现程序，从中可以看到锁相环的基本功能的实现。-This program is a simple phase locked loop of MATLAB implement programs, from which you can see the basic function of phase-locked loop of implementation.
mydesign_DPLL
- 实现了数字锁相环设计，可以用于信号的时钟提取供本地时钟使用-the design introduced a method to use DPLL,we can get the local clock from the signal
a-new-digital-PLL
- 基于FPGA实现的一种新型数字锁相环设计。该设计是用VHDL来实现的，个人觉得不错，所以传上来和大家分享-FPGA-based implementation of a new digital PLL design. The design is to use VHDL to implement the individual feels good, so come and share transfer