搜索资源列表
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
half_float-master
- half_float: C implementation of a 16 bit floating-point type mimicking most of the IEEE 754 behaviour. Compatible with the half data type used as texture format by OpenGl/Direct3D.
SVM
- State vector machine with single class output. The code works on 32 bit numbers in IEEE 754 floating point format for single precision numbers.
VHDL-Samples
- VHDL Samples，8-bit calculator controller；vending machine controller with typical vending machine logic ；mplements (most of) the logic required to implement a IEEE 754 multiplier unit.
floatConvert
- 根据IEEE754规定写了个float型数据与二进制数转换的方法-According to the provisions of the IEEE 754 wrote a float data and binary conversion method
Numeric-754
- WYD Numeric Source v754
adder
- 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
Coding Files
- Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double
Source
- wyd you from clientpatch version 754