搜索资源列表
leon3-altera-ep2s60-sdr
- ahb sdram interface.arm cpu series,include controller
ahb_system_generator.tar
- An AHB system is made of masters slaves and interconnections. A general approach to include all possible \"muxed\" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a mas
SLAVERAM
- AHB slave 的一个简单的原型程序，通过参考该程序，可以写出相应的ahb slave 代码
ARM_SPI
- arm spi寄存器的使用方法实例，各种初始化寄存器使用方法等-arm spi register to use examples
LIP1201CORE_dll
- Verilog DLL sOURCE CODE
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
ahbapb
- AMBA2.0标准的AHB2APb桥，代码通过验证-AMBA2.0 standard AHB2APb Bridge, through the verification code
ahb_master
- AHB总线接口描述，MASTER的接口描述，AMB总线协议(AHB bus interface descr iption, MASTER interface descr iption, AMB bus protocol)
ahb_system_generator_latest.tar
- amba ahb master generator by using verilog
ahb_sramc_svtb
- ahb总线Verilog代码及sv仿真文件(ahb bus Verilog code and sv simulation code)
ahb_sramc_vtb
- ahb总线Verilog代码及Verilog仿真文件(ahb bus Verilog code and Verilog simulation code)
AHB
- AHB_Verificaion_Code
ahb2apb-master
- ahb to apb master and slave
ahb2apb_bridge_verification-master
- ahb to apb master verification
ahb_task
- ahb接口的sram做读写测试的读写时序(SRAM of the AHB interface for reading and writing tests)
AHB
- 基于amba总线协议中的ahb总线的从机模块代码,需要modelsim进行测试仿真(Based on the slave bus module code of AHB bus in AMBA bus protocol, Modelsim is needed to carry out test simulation.)
dma_ahb_latest.tar
- AHB DMA verilog源码 AHB总线 DMA接口源码(AHB bus DMA interface source code)
AHB2-master
- verilog ahb master and slave
AHB2-master
- AMBA AHB 2.0 VIP in SystemVerilog UVM
基于ahb总线的sramc设计与验证（SV，uvm）
- 基于ahb总线的sramc设计与验证（E课网）