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DDS小数分频
- 文件列表(点击判断是否您需要的文件,如果是垃圾请在下面评价投诉): DDS小数分频 ...........\Block1.vhd.bak ...........\db ...........\..\add_sub_9mh.tdf ...........\..\DDS.asm.qmsg ...........\..\DDS.asm_labs.ddb ...........\..\DDS.cbx.xml ...........\..\DDS.cmp.
利用C8051F340单片机对DDS芯片AD9834进行编程
- 利用C8051F340单片机对DDS芯片AD9834进行编程,产生方波和三角波,A C8051F340 program to generate square and triangular waves with the DDS chip AD9834
基于FPGA的直接数字频率合成器(DDS)设计
- 基于FPGA的直接数字频率合成器(DDS)设计 (源程序),FPGA-based direct digital synthesizer (DDS) design (source code)
DDS.rar
- DDS信号发生器,利用VHDL实现,可根据频率控制字的改变输出不同频率的信号,最高可到达10MBPS,DDS signal generator, the use of VHDL realization of frequency control word in accordance with changes in output signals of different frequencies, the maximum arrival 10MBPS
DDS.rar
- 自己在Quartus下用VHDL编写的一个DDS程序。包括寄存器,累加器,波形存储器,In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
DDS(AD9850)C语言代码实现直接频率合成
- DDS(AD9850)C语言代码实现直接频率合成,另带人机交互界面,code for AD9850
dds(heli).rar
- DDS用verilog 实现,可以实现方波、正弦和三角,DDS using verilog realized, can be square wave, sinusoidal and triangular
DDS.rar
- 基于EPM7128的数字合成信号发生器(DDS)设计。通过对EPM7128编程,组合出地址累加器、数据锁存器、256*8位ROM空间。外接DA可实现正弦波输出功能,EPM7128-based signal generator for digital synthesis (DDS) design. EPM7128 through programming, the combination of address accumulator, data latches, 256* 8 ROM space.
dds.zip
- 在opengl下加载DDS纹理文件的源程序,支援DXT-1,DXT-3和DXT-5等标准。,Under the load in the opengl texture file DDS source code, support DXT-1, DXT-3 and DXT-5 and other standards.
DDS.rar
- Quartus中实现的DDS 使用的是altera提供的IP core,DDS achieved Quartus using IP core provided by altera
DDS-top.rar
- 能够基于DDS实现输出正弦波形的一部分程序,利用Verilog HDL语言编写。,Able to achieve based on the DDS output sine wave-shaped part of the procedure, the use of Verilog HDL language.
DDS
- 基于quartus的DDS,可以发生正弦波,方波,三角波,附带了顶层文件,注释在程序中-Quartus on the DDS, can occur sine wave, square wave, triangle wave, with the top-level documents, notes in the procedure
dds
- verilog 硬件语言实现DDS,使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
DDS
- 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wa
51-DDS
- 基于51单片机 DDS 的信号发生器设计 (有源代码)-51 MCU-based design of DDS signal generator (source code)
dds
- 基于FPGA的DDS设计,本程序采用verilog HDL语言编写,使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
DDS
- DDS文件夹内的程序,完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
FPGA-DDS
- 在FPGA内,以查表方式实现频率直接合成器(DDS)功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
dds
- verilog语言编写,在Quartus II里仿真DDS的产生,包括所有仿真生成的相关文件,-verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
FPGA-VHDL-DDS
- 基于FPGA的DDS波形发生器--程序,如果需要产生输出不同的位数的波形,可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom