搜索资源列表
verilogpll
- 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
PLLpro
- 关于数字锁相环的使用，结合FM,AM的使用来说明-DPLL on the use of combined FM and AM to illustrate the use of
pll_improvement
- 一种改进的全数字锁相环设计 一种改进的全数字锁相环设计-an improved DPLL design an improved design DPLL
VHDLDPLL
- 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
dpll0227
- DPLL同步提取有一定效果-DPLL simultaneously extract a certain effect 11111111111111111111111
chip1
- CPLD的程序,分频,微分等,应用于DPLL -CPLD procedures, frequency, differential, etc. can be applied to DPLL
dpll0226
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
DPLL0227+V+qt6
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
pll1218
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
digital_loopback
- 基于ti公司6713dsp的数字锁相环，运行环境为ccs3.1。希望有所帮助。-ti-based company 6713dsp the DPLL, the operating environment for ccs3.1. Want some help.
all_digital_phase_locked_loop
- 一篇关于数字锁相环的很好的文章，费了很大力气才搞到的-a DPLL on the good paper, and a great effort will involve the
5509aUSBAPLL
- 5509A usb模块由默认的DPLL转向AP-5509A module usb default by the DPLL to AP
dpll
- 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，
FPGA-DPLL
- 基于FPGA实现的一种新型数字锁相环
数字锁相环
- DPLL
verilog dpll（数字锁相环）
- 用xilinx ise 10.1实现了数字锁相环，仅供参考
PLL_grt_rtw.rar
- C语言实现了数字锁相环的程序，不过程序比较复杂，得参照MATLAB中 Discrete 3-phase pll模型,C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model
NCO_sin
- 介绍了压控震荡器(VCO)的设计，压缩包里面有VHDL语言编写的代码，在仿真器上可以实现仿真结果，非常不错 -The VHDL code of VCO
DPLL
- 90度锁定的数字锁相环的设计的VHDL源代码-The VHDL code of Digital Phase-Locked Loop Based on CPLD
45370466
- 基于vhdl语言描述的dpll，以及图片-Based on the VHDL language is described dpll, as well as the picture