搜索资源列表
FIFO
- 用VHDL语言编写的实现FIFO的设计，经编译下载成功
页面置换算法（FIFO和LRU）
- 模拟操作系统虚拟存储中的页面置换算法采用FIFO算法和LRU算法-simulation operating system virtual memory pages the algorithm used FIFO replacement algorithm and LRU algorithm
fifo源程序
- fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
异步FIFO的VERILOG实现（格雷码）
- 使用格雷码实现异步FIFO
IDT FIFO 控制代码
- IDT FIFO的Verilog控制读写代码
实用verilog代码（乘法器，触发器,FIFO等）
- 本文件包含一些实用verilog程序代码，包括乘法器，除法器，伽罗瓦域乘法器，CORDIC数字计算机的设计，异步FIFO设计，伪随机序列应用设计，RS(204,188)译码器的设计，都是可综合的。对研究这部分的朋友有一定的帮助。
CY7C68013读写FIFO源代码
- CY7C68013读写FIFO源代码（Verilog）,已测试
fifo的FPGA实现
- fifo的FPGA实现
DC_FIFO
- DC_FIFO 是异步fifo
初始化USB控制芯片，实现FIFO模式传输代码
- 初始化USB控制芯片，实现FIFO模式传输-Initialize the USB controller chip, the FIFO mode transfer
serial.rar Dos 串口通信例程实现了FiFO
- Dos 串口通信例程实现了FiFO ,中断发送中断接受！,Dos serial communication routines to achieve a FiFO, interrupted send interrupt accepted!
CCD.rar
- CCD数字相机的全代码，DMA方式读取FPGA，FIFO送入计算机，网口跑UDP协议,CCD digital camera the entire code, DMA mode to read FPGA, FIFO into the computer, I run UDP network protocol
FIFO
- 进程调度算法有FIFO，优先数调度算法，时间片轮转调度算法，分级调度算法，把各种算法用C语言实现-Process scheduling algorithm FIFO, priority number scheduling algorithm, time slice rotation scheduling, hierarchical scheduling algorithm, the various algorithms using C language
fifo
- FIFO 是一种先进先出数据缓存器，这是一个同步FIFO的VHDL源程序，将FIFO分成几个模块进行设计，最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
FIFO
- FIFO设计的难点在于怎样判断FIFO的空/满状态。为了保证数据正确的写入或读出，而不发生益处或读空的状态出现，必须保证FIFO在满的情况下，不能进行写操作。在空的状态下不能进行读操作。怎样判断FIFO的满/空就成了FIFO设计的核心问题。-FIFO design challenge is how to decide the FIFO empty/full. In order to ensure the correct data is written or read, or read the b
FIFO.rar
- 一个操作系统试验 虚拟存储器页面转换FIFO算法模拟实现,An operating system virtual memory page test conversion FIFO algorithm simulation
SCI_FIFO.rar
- F2812 SCI FIFO中断发送和接收例程,F2812 SCI FIFO interrupt routines to send and receive
Verilog_CY7C68013-SLAVE-FIFO
- 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
FIFO-LFU
- 用C语言实现操作系统请求页面调度算法FIFO LFU的实现 提前装入0，5,6页最后能够计算出缺页中断率-Operating system using C language the page is requested the implementation of scheduling algorithms FIFO LFU advance into 0,5,6 page last page fault rate to calculate the vacancy
fifo_32_4321.rar
- 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit，输出数据可以配置为4-1任意bit。有设计文件和testbench,Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench