搜索资源列表
CPU_test
- 设计并通过modelsim仿真软件实现了一个可以在FPGA平台上运行的8位RISC的CPU软核-Design an 8-bit RISC CPU soft core on an FPGA platform and simulate it using ModelSim
实例模块
- 各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench
wb_switch
- wb_switch，opencore，精简指令cpu设计-wb_switch，opencore，risc cpu design。
sw_leds
- 精简指令cpu设计，外扩电路设计，led开发板驱动-wb_sw_leds，opencore，risc cpu design。
display-seg
- 七段数码管驱动电路，fpga，seg7，altera开发板例子-risc-cpu design，seg7，fpga
risc_cpu
- SystemC实现的一个精简指令CPU模型-risc CPU model in systemc
RISC_CPU
- 本例子是一个精简指令集CPU，非常好用经过测试-This example is a RISC CPU, very handy tested
Chapter-13
- 13.2 RISC-CPU设计 13.3 RISC-CPU Testbench设计-13.2 RISC-CPU design 13.3 RISC-CPU Testbench Design
cpu
- RIsc 处理区 内附仿真文件和相关报告-RIsc treatment area containing a simulation files and related reports
all_cpu
- 精简指令集CPU，可完成移位，跳转等简单功能，适用于FPGA学习，本代码使用verilog编写。-RISC CPU, to be completed by the shift, jumps and other simple functions for FPGA learning to write the code using verilog.
TCAM_2
- 经典RISC CPU 设计，和PCI8位指令单片机兼容，值得初学者看一下-Classic RISC CPU design, and PCI8 bit microcontroller compatible instruction, it is worth a look for beginners
DLX_verilog
- DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
CPU
- 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware descr iption language developm
RiscCpuA
- systemC模仿RISC CPU的简单功能-system C foumulate the simple function of RISC CPU
RiscCpuB
- systemC模仿RISC CPU的一般功能-systemC imitate RISC CPU' s general functions
RiscCpuC
- systemC模仿RISC CPU的完全功能，包括时序，信号-systemC imitate fully functional RISC CPU, including the timing, signal
openfire_core_latest.tar
- openfire实现 microblaze机构的cpu代码,RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡-openfire complete microblaze architecture cpu,RISC CPU Verilog sourcecode and documents
risc8
- 八位简易risccPU，采用verilog描述，FPGA实现-8bit risc CPU
RISC_CPU
- RISC cpu设计，verilog语言，PIC14位指令集-RISC cpu design, verilog language, PIC14-bit instruction set
RISC_CPU_matlab
- RISC处理器的matlab代码，里面每个模块划分都很细致，是 FPGA设计RISC处理器的重要参考-RISC CPU DESIGN