搜索资源列表
keyscan
- 利用VHDL语言编写的4*4键盘扫描程序，经过测试，可以放心使用。-Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.
CLK_TEST
- VHDL实现的8分频程序，经测试，在板上运行成功-8 divided clock
dds_test
- 用来测试DDS程序的，使用的芯片是9854，语言为VHDL，里面含有测试结果图，对需要的朋友非常有用-DDS program used to test the chip using a 9854, language VHDL, which contains test results chart is very useful for a friend in need
seq_detector
- 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test so
m
- 这是vhdl编写的产生7位m序列的程序，类比可以产生更多为的。而m序列即可作为输入测试信号，也可以模拟噪声。-It is written vhdl 7 m sequence generation process, can produce more for the analogy. The m-sequence can be used as an input test signal, it can simulate noise.
hough_5289
- hough变换的vhdl程序设计，测试没有任何问题，可以执行，开发工具quartus，modelsim-hough transform with fpga and vhdl ，good tested and you can use it happily
Serial-port-sending
- 基于FPGA的串口发送程序，用VHDL语言编写，采用状态机的方法，可用串口调试软件进行测试-FPGA-based serial port procedures, using VHDL language, using the state machine approach can be used to test serial debugging software
counter9
- 运用VHDL输入方式设计一个0-9之间的减1计数器，完成程序的编译、综合、仿真测试，并给出仿真波形-Design using VHDL input between minus a 0-9 counter, complete compilation, synthesis, simulation, test procedures, and gives the simulation waveforms
FSK_MODULATION_DEMODULATION_CODE
- FSK调制与解调VHDL程序_好用_测试正确-FSK modulation and demodulation of VHDL program _ with _ test correctly
MASK_MODULATION_CODE
- MASK调制VHDL程序_好用_测试正确-The MASK VHDL program with _ _ modulation test
MPSK_MODULATION_DEMODULATION_CODE
- MPSK调制与解调VHDL程序_好用_测试正确-MPSK modulation and demodulation of VHDL program _ with _ test correctly
URAT_VHDL_CODE_TEST_OK
- URAT VHDL程序_好用_测试正确,项目已使用-URAT VHDL program _ with _ test correctly
ASK_modulation_code
- ASK调制VHDL程序，好用，已测试通过-ASK modulation VHDL program, easy to use, has been tested
CPSK_modulation_code
- CPSK调制VHDL程序，测试正确，已使用-CPSK modulation VHDL procedures, the test is correct, has been used
led_river
- FPGA实验，基于VHDL语言的流水灯程序设计，采用分模块设计思路。下载到板子上测试通过。-FPGA experiment, water lamp program design based on VHDL language, using modular design train of thought.Downloaded to the board on the test pass.