搜索资源列表
AMBA
- 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
mcb_read_write
- 赛灵思 DDR2 用户接口程序 原创。希望对各位有用。-Xilinx DDR2 original user interface program. You want to be useful.
Xil3SD1800A_MIG
- 基于xc3sd1800afg676的开发板的DDR2的控制器的IPCORE，提供完整的代码和UCF。系统时钟频率为125Mhz。-The development board based on xc3sd1800afg676 DDR2 controller of IPCORE, provide a complete code and UCF. System clock frequency of 125Mhz.
DDR2PCBLayout
- TMS320DM643X系列DDR2的PCB布局-Implementing DDR2 PCB Layout on the TMS320DM643x
DDR SDRAM Design Tutorials
- Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
the_design_and_realization_of_DDR2-SDRAM_controlle
- ddr2控制器的设计与实现,详细介绍了其结构和思想-the design and realization of DDR2-SDRAM controller
DDR2_controller
- DDR2控制器IP的设计与FPGA实现，使用verilog语言-DDR2 Controller IP Design and FPGA implementation, use the verilog language
mt48lc16m4a2
- DDR2 仿真模型 DDR2 仿真模型-DDR2 Simulation Model
ssss
- spartan—3a对ddr2读写控制源程序，有verilog和vhdl版本-spartan-3a ddr2 read and write control of the source, there are versions of verilog and vhdl
ddr2_test
- 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
AllegroDDR2
- DDR2讲座allegro 资料不错 可以下载学习-DDR2 PPT reference 资料不错 学习
OK16bit
- 16BITS DDR2原理图 讲解 详细 学习用
PC2-6400_PC2-UDIMM
- 三星的DDR2内存PCB设计文件；ALLEGRO文档格式；-Samsung' s DDR2 memory PCB design document ALLEGRO document format
user_design
- spartan3a-ddr2 (16bits 333M)
ddr
- 利用硬件verilog语言实现DDR2功能，对信息快速存储-VERILOG DDR2
1024Mb_ddr2
- DDR2的Verilog仿真代码，可以使用ModelSim仿真-DDR2' s Verilog simulation code, you can use the ModelSim simulation
DDRCHv11
- Source code for ddr2 dram controller for BEEE
Virtex-5-FPGA_DDR2_SDRAM_data
- Virtex-5 FPGA实现的高性能 DDR2 SDRAM数据采集，需要对V5有一定基础的人学习-Virtex-5 FPGA DDR2 SDRAM to achieve high-performance data acquisition, the need for V5 have to learn some basic
DDR2-verilog
- Verilog程序设计实例中，DDR部分的程序代码-Verilog programming example, DDR part of the program code