搜索资源列表
DDS
- 基于FPGA的DDS直接信号合成器，基于Altera CYcloneII系列-DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
dds
- 基于vhdl的dds信号发生器，可产生方波，三角波，正弦波，幅度，频率，相位可调-The signal generator based on VHDL DDS, can produce square wave, triangle wave, sine wave, amplitude, frequency, phase can be adjusted
DDS
- 关于用FPGA制作的DDS源代码。用的是verilog语言，用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
quartus-dds
- quartus环境下利用原理图方式实现DDS的图文教程，主要掌握原理图输入，quartus仿真功能-quartus environment using the schematic approach of DDS graphic tutorial, the main control schematic, quartus simulation
DDS-9850
- 基于9850和AVR单片机的DDS波形合成 很简单的教程 以及各种论文-Based on 9850 and AVR microcontroller DDS waveform synthesis is very simple tutorial and various papers
DDS
- 基于STM32库函数的DDS函数输出器.绝对可以运行试验-Base on the ADS9852 and Stm32-----DDS.
DDS
- 能在DDS中用Verilog HDL语言实现FM,AM,FSK,ASK,PSK，结合可编程器件FGPA等等就能实现这些功能 -DDS can be used in Verilog HDL language FM, AM, FSK, ASK, PSK, etc. FGPA programmable devices can be combined to achieve these functions
DDS
- 这个是在quartusii和matlab simulink下搭的dds的模型，已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
DDS-in-Verilog
- Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
DDS
- verilogHDL语言编写，带测试文件DDS波形发生器.-DDS waveform generator, verilogHDL language, with the test file
AD9834-DDS-C51
- 基于AD9834 DDS芯片的驱动程序 实现宽带宽波形输出-Based on the driver AD9834 DDS chip to achieve wide bandwidth waveform output
DDS
- DDS功能仿真，用MATLAB仿真DDS功能，通过控制频率控制字实现不同频率正弦波的输出。-DDS functional simulation, using MATLAB simulation DDS functions, by controlling the frequency control word different frequency sine wave output.
Verilog-dds
- 用Verilog实现的DDS，直接频率合成器，相位可调。-Verilog DDS generator
dds
- DDS信号的产生程序，以及DDS相关文章，综合报告。-DDS signal generation procedures and the DDS articles, comprehensive reports.
DDS
- 基于dds原理产生频率信号,输入一个基准信号即可产生任意高于其频率的信号(Generation of frequency signals based on the DDS principle)
DDS
- DDS的字长决定了正弦/余弦基准信号样点的个数和所产生频率信号的量化精度。 最小频率间隔决定了DDS所能产生信号的最小频率。DDS所产生信号的频率为最小频率间隔的整数倍。(The word length of the DDS determines the number of sample points of the sine / cosine reference signal and the quantization accuracy of the generated frequency si
DDS 信号模块AD9850模块资料
- DDS 信号模块 AD9850 模块资料(DDS signal module, AD9850 module data)
dds(1)
- 基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
DDS波形发生器
- DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)
DDS
- 用FPGA实现的DDS，用法简单，波形稳定(DDS is implemented using FPGA)