搜索资源列表
DDS.rar
- Quartus中实现的DDS 使用的是altera提供的IP core,DDS achieved Quartus using IP core provided by altera
pci.tar.gz 完成WB BUS和PCI bus之间的传输
- verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输,The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transact
PWM_LED.rar
- 基于ALTERA公司NIOSII的LED灯控PWM IP核设计,ALTERA-based company controlled NIOSII the LED lamp PWM IP-core design
PCI-IPcoreor1k[1]
- PCI的ip core，VHDL代码，希望对大家有帮助-PCI-ip core, VHDL code, we hope to help
aes_inv_cipher_top
- aes ip core, 128 bits
FFT_verilog
- verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
pwm
- 在Quartus 9.0 下实现的PWM IP核设计，周期占空比均可调。-PWM IP core design,which period and duty is adjustable.
10100MIP
- 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码，可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
IP
- ALTERAL的stratix4的IP核的使用讲解PPT，便于理解Stratix的IP核调用-The IP core stratix4 ALTERAL the use to explain the PPT, to facilitate the understanding the Stratix of IP core call
q_sys
- PCIe ip核。使用Quartus II 11.0，在Altera开发板4cgx15上验证通过。-PCIe ip core. Using the Quartus II 11.0, in the Altera development board 4cgx15 verify through.
8051_ip_core
- 8051微控制器的ip 核的vhdl源代码,其中包含了相应的测试程序.-8051 micro-controller ip nuclear vhdl source code, which contains the corresponding test procedures.
29becbce-7f76-454c-9f85-fb6138f83375
- cpu IP 核设计的verilong代码-cpu IP core design code verilong
photo_verilog
- verilog开发的电子相册系统，是基于Altera的FPGA芯片和IP核的设计！-Verilog developed electronic album system is based on Altera s FPGA chip and IP core design!
BaselineJPEGSoftwareCodecCodes
- In term project, we will take the baseline JPEG codec in ARM-based platform system as an example to practice the design flow in SoC. We divide the project into three parts, and the goal of each part is described as follow. Part I: Design a baseli
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
VERILOG_VERSION_PIC16C57
- VERILOG VERSION PIC16C57 是一个用于FPGA模拟PIC16C57的IP核，有帮助文件，介绍了如何测试使用这个IP核。用VERILOG语言编写的。-VERILOG VERSION PIC16C57 is a PIC16C57 for FPGA simulation of the IP core, has helped document describes how to test the use of the IP core.
FPGA_8008
- pci pci转local bus总线的应用，使用IPcore alter器件-pci pci convert local bus application,use alter IP core
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES