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clk_div2
- 本源码是分频器的VHDL,在QUARTUS2下已进行仿真和验证，-The source is the divider of the VHDL, have been carried out under the QUARTUS2 simulation and verification,
model
- 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
jk
- 基于quartus2的jk触发器设计，内含源码和仿真图-Jk flip-flop design based on the quartus2, containing source code and simulation diagram
quartus2qq
- 这里是对PFGA的软件Quartus2的介绍，并以其他方式来分析。更全面的了解这个软件-Here is PFGA software Quartus2 introduction, and in other ways to analyze. More comprehensive understanding of the software
quartus2
- quartus 2 软件学习资料，为处学者提供详细的软件操作及其编程语言介绍-Quartus 2 software, learning materials, for scholars Department provide details of the software and its programming language introduced
FPGAkeshe.doc
- 基于FPGA/CPLD的以QUARTUS2 的能够实现交通灯的显示与控制-enable the lingting traffic display
VerilogHDLREV1.1
- verilog入门级书籍：帮助更好的理解verilog语言及操控quartus2软件：verilog那些事,来自黑金开发板原文资料-Verilog entry-level books: help better understand verilog language and control quartus2 software: verilog those things, gold development board from the original material
quartus2
- 这是一本quartusII的中文经典教程，内容丰富，讲解详细，非常值得一看-This is a quartusII Chinese classic tutorials, rich in content, the explanation is detailed, extremely is worth a look
vga_dis
- verilog语言实现VGA接口显示，可以在显示器上显示几种图片，可以直接在quartus2上运行-verilog language display, VGA interface can display several pictures on the monitor, you can run directly in quartus2
sin-to-mif
- 正弦信号发生器生成正弦信号 存储格式为mif 用于quartus2的仿真-Sinusoidal signal generator to generate a sinusoidal signal storage format for the mif for quartus2 simulation
multiplier
- 8*8的乘法器基于quartus2的显示文件，其中使用了门电路和全加器来实现的，全加器用以实现进位运算，由于是第一次上传文件，这个是基于quartus2的显示文件-8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations
VFIFOzipe
- 用verilog实现异步FIFO，代码中有两个模块，使用时时注意顶层模块和底层模块，用quartus2即可打开直接使用。 -Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
vFFPPGAproe
- VERILOG HDL 实际工控项目源码开发工具 alltera quartus2 -VERILOG HDL practical industrial projects source code development tools alltera quartus2
VHDL8259_relize
- 一个使用vhdl语言实现中断控制器8259a的例子，注释很详细，经过quartus2验证成功-An example interrupt controller 8259a vhdl language, very detailed notes, after quartus2 verify success
epcverilogTimer
- 用verilog编写的epc的仿真定时器。用quartus2 仿真-Epc prepared with verilog simulation timer. Simulation with quartus2
quartusii
- 本文档介绍quartus2的使用过程，是初学的入门的好参考资料-quartus
intro_to_quartus2_chinese
- 这个是介绍CPLD/FPGA的开发环境quartus2的文章，对初学者及开发人员应该会有一定的帮助。-This is to introduce the CPLD/FPGA development environment quartus2 in the article, there should be some help for beginners and developers.
c0_led
- VHDL编写的时钟程序 用于alter实验板 编写程序为quartus2-Clock program written in VHDL is used to alter the experiment board programming for quartus2
eda
- 74LS283的4位BCD码加法器,用quartus2编译，有详细的电路图-74LS283 4-bit BCD counter
Verilog-code
- 基于cyclone 内核的fpga的源代码，带quartus2下载文件-Based on the source code of the cyclone kernel fpga, with quartus2, download files