搜索资源列表
CPUverilog
- pic cpu source code. it is writed in the verilog source code. it can work on the 40Mhz high speed.
ccpu
- 这个是用VERILOG做的一个8位功能很弱的CPU-this is a done VERILOG eight functional weak CPU
riscdesign
- 一个非常简单的cpu设计的原代码,是用verilog编写的-a very simple cpu design of the original code, was prepared by the Verilog
Cpu_model
- Verilog HDL编写的CPU模型,很经典,比较通用-Verilog HDL prepared by the CPU model, classic, more generic
simple_cpu
- 初学cpu结构的很好的verilog代码的示例,适合初学者-novice cpu structure of the good verilog code examples for beginners
leg_source
- verilog hdl编写,六段流水线CPU.程序完整,功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
riscmcu
- 精简CPU设计,需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
RISC_Core.ZIP
- 这是一篇关于8位RISC CPU设计的文章,其中包含了用Verilog语言编写的CPU内核程序
minirisc.tar
- verilog code .descrip the risc cpu.download from opencores.org
ALU
- 用verilog编写的32位alu部件,用于cpu制作
The_6th
- 一个自己写的8位CPU程序,以Verilog语言实现,仅可做8×8的乘法和8/8的除法,功能不强大,但对于初学Verilog的人应该有些帮助
simple_MCU
- 设计CPU方法及流程!VERILOG hdl
PicoBlaze_Embedded
- verilog语言编写,ISE8.2开发的,基于8位cpu PicoBlaze的程序
simu_NIOS
- 和NIOS功能一样的CPU,可以在FPGA上运行,Verilog源代码
VeriRiscCPU
- 这个文件中使用verilog hdl简单的利用基本运算实现了微型的cpu设计开发过程
simplecpu
- 一个16位简单CPU的Verilog源代码。
CPU_interface_verilog_code
- 包括一个基本的CPU接口的verilog程序及激励程序。
ethernet_verilog
- 这是一个很好的Verilog 编写的8位RISC CPU源码(可做为MCU),并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
MYCPU2.0
- 用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU
risc_cpu
- 这是一个Verilog HDL编写的RISC cpu的程序,该程序共10个子程序,实现了简单的RISC cpu,可供初学者参考,学习硬件描述语言,及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this e