搜索资源列表
AD[TLC549]
- AD[TLC549] ：采集模拟输入，电压动态显示在数码管(用verilog实现)-AD [the TLC549]: the acquisition of the analog input voltage dynamic digital tube (Verilog)
ad
- ad采样程序，Verilog HDL，实测可用-ad sampling procedures, Verilog HDL, measured available
1602test
- Verilog AD转换1602显示，用QuartusII编写的。完整的工程，好使！-Verilog AD converter 1602, with QuartusII prepared. Complete works, so that!
AD
- 控制AD7934的信号verilog,控制AD7934的信号verilog-control the ad7934
adc_test
- verilog AD采样源代码，包括test代码-verilog AD
Quartus
- VERILOG AD采集程序 FIFO存储-VERILOG AD acquisition program FIFO memory
AD
- 基于FPGA的AD采集系统 用verilog编写 基于basys2开发板-FPGA AD verilog basys2
yuanma
- 介绍了fpga开发的的数个工程源码，包括按键，时钟，AD/DA，VGA，数字示波器等(Introduced FPGA development of several engineering source code, including buttons, clock, AD/DA, VGA, digital oscilloscope, etc.)
ADM_code
- AD采样转换,采用verilog完成，可直接使用。(AD TRANSMIT using verilog complete, can be used directly.)
DA_AD_v1.1B
- AD DA程序测试已经通过。12位分辨率 500KHz的AD和DA(Program test has passed by AD and DA with 12 bits resolution ratio in 500HZ frequency)
SMG
- 实现将BCD码动态扫描显示在数码管上--verilog(The realization of dynamic scanning BCD code displayed on the digital tube --verilog)
ad_prj1.4.3
- AD采集固定点数FPGA对采集数据进行指定次数累加，存储至片外SRAM并等待上位机发送取数据指令(The AD acquisition fixed point number FPGA adds the number of data to the collected data, stores it to the outside SRAM and waits for the upper computer to send the data instruction)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
FPGA verilog代码
- ad转换模块hx711用FPGA的驱动实现(hx711 FPGA aaaaaaaaaaaa)
28_adda_test
- 在Quartus平台上，完成了AD、DA的Verilog实现，测试结果准确。(Use Verilog to realize the function of AD and DA)
ad73311
- AD73311芯片的控制和数据程序，用于控制音频AD芯片。(AD73311 chip control and data program)
A4_Da_Top
- 利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(The simple oscilloscope is realized by using AD, DA and VGA peripherals. The DA peripheral sends sine wave to the AD peripheral, and the AD peripheral res
down_up_dds
- 在Vivado下完成AD输入到下变频的功能，频率可配置，通用化设计。(The function of AD input to down conversion is completed under Vivado, and the frequency is configurable and universal design.)
adc_interface-master
- ADC_Interface Simple SPI interface for AD7908/AD7918/AD7928 written in verilog HDL
test_ADC
- verilog 数模转换程序，包括AD与DA，AD能够对于波形的数值进行输出，使用的是ego1开发板(transition of A/D signal)