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Simulation
- This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (R
最常用的卷积码的维特比C程序viterbi-3.0.1.tar
- 维特比译码的C程序，专门用于卷积码的解码！希望对大家有所帮助！-Viterbi decoding C program devoted to convolutional code decoder! We want to help!
viterbi_fpga
- viterbi译码器的一种fpga实现.是一个cs252 的project的result 供大家研究用-Viterbi Decoder they simply a realization. Cs252 is a result of the project for all research
Viterbidecoder
- 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
viterbi_wlan_c54
- viterbi译码在DSP上的实现,采用c54x-Viterbi decoder on DSP Implementation, adopted c54x
weite
- 这是维特比译码器的编程，是我自己编的，可以给做设计的人一点参考-This is the Viterbi decoder programming, is my own series and can do a design point of reference
encoder_and_viterbi_decoder_for(213)_convolutional
- 压缩包内为本人写的(2,1,3)卷积码编码器和维特比(viterbi)译码器.编码器和译码器分别封装在一个类中,每个类的方法和变量均有注解-compressed I write for the (2,1,3) convolutional code encoder and Viterbi (Viterbi) decoder. Encoder and Decoder were packaged in a category, each class methods and variables have
ViterbiFPGA
- 论文格式，内含Viterbi编解码器的完整vhdl代码，文件为.nh格式-paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format
IS-95basebandsimulation
- This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RR
SKRETD(low_power)
- 硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
VIT2.1.6
- viterbi 编译码器C源程序，rate=1/2 N=7-Viterbi Decoder C source, rate = 1 / 2, N = 7
viterbi_decoder_spw
- Cadence SPW 4.8.2，viterbi解码的源码。-Cadence SPW 4.8.2, the Viterbi decoder source.
viterbi213
- 提供了一个硬判决的viterbi译码器（2，1，3） 有源程序及算法描述，未成定稿，只供参考 （vhdl 语言描述） -provided a hard decision of the Viterbi Decoder (2,1, 3) the source code and the algorithm descr iption, from his position as final, for reference (vhdl Descr iption Language)
c5wup37s
- 卷积码编码，维特比解码程序，用c写的。应该有人需要-convolution encoder, Viterbi decoder, and c writes. Someone should be required
VDK9R12
- viterbi译码器（2.1.7），里面什么都有，测试模块，编码模块和译码模块-Viterbi Decoder (2.1.7), which has everything, testing modules, Encoding and decoding module module
deconvgaijin
- 卷积码译码算法改进 实现Conv.(2,1,9)的编码、软判决滑动窗维特比译码，其生成多项式为G0=561(八进制),G1=753(八进制)，调制方式为BPSK，信道为AWGN，比较不同的译码深度对译码器性能的影响-convolutional code decoding algorithm to improve achievement Conv. (2,1,9) of the Code, Soft Decision sliding window Viterbi Decoder, genera
IS95_baseband_simulation
- his packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RRC
convcode0.1
- 卷积码编码器，与对应的维特比硬判决译码器。已经通过仿真验证-Convolution Encoder, and the corresponding hard decision Viterbi decoder. Has been verified by simulation
viterbi_decoder_sources_code_verilog
- viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
Soft_decision_Viterbi_Decoder
- 该代码为Viterbi Decoder C/C++源程序。现为Doc文件。所含的vdsim.h在最后。-the Viterbi Decoder code for C / C source files. Doc is the document. Vdsim.h contained in the final.