搜索资源列表
C2
- 功能更加完善的基于vhdl的数字时钟设计 有秒表,时钟,时期,闹钟的功能和整点报时,时间调整,日期调整,闹钟的设定 、、、、、、、 秒表有开始,暂停,清零等功能,且只有在暂停的情况下才能清零。
watch
- 功能更强大的数字时钟,有年份,月,日,时,分,秒和星期,可以调校-More powerful digital clock, there are years, months, days, hours, minutes, seconds and weeks, you can adjust the
sheji2
- 一个秒表的硬件设计,学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
24
- 简单的数字时钟EDA设计,并通过电路的仿真和硬件验证,进一步了解计数器的特征和功能。-Simple digital clock EDA design, and through circuit simulation and hardware verification, and further understanding of the characteristics and functions of counters.
clock
- 本文档采用VHDL语言编写了一个数字时钟的程序,该数字时钟采用24小时制计时,可以实现整点报时,时间设置,闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clo
DDSckkc
- 以把直接数字频率合成(DDS)看成这样一种技术,它能用数字值形式的信号控制正弦波的频率。最简单的DDS电路包括一个二进制计数器,一个以等间隔正弦波值进行全波编程的ROM,以及一个数模转换器,用于将存储的正弦波值转换为电压。计数器的时钟频率决定了正弦波的频率,但这 -To the Direct Digital Synthesis (DDS) as such a technology, it can use the digital value of the form of the frequen
Sequencedetector
- 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号,这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后,若这组码与检测器中预制的码相同,输出为A,否则输出为B。序列检测I/O口的设计如下:设Din是串行数据输入端,clk是工作时钟,clr是复位信号,D是8位待检测预置数,QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets consisting of binary code from the
3FSK.vhd
- 利用MAXPLUS作为仿真工具,用VHDL语言编程,采用频率键控法实现3FSK调制。对输入的系统时钟分别进行2分频,4分频和8分频得到这3种频率。通过对数字基带信号进行双二进制编码得到3个电平值,把它们作为三选一开关,来分别选择不同的频率值、选择不同的信号,从而实现3FSK调制。-As a simulation tool used MAXPLUS using VHDL language programming, using frequency shift keying modulation me
digital_clock
- 一个关于数字时钟设计实现的VHDL源代码,已测试过,可以运行-Design and implementation of a digital clock on the VHDL source code has been tested, you can run
eda
- eda实验时钟电路系统由秒时钟产生电路、走时电路模块、数字显示模块、校时模块、语音报时模块、工业控制模块-eda test clock circuit generated by the second clock circuit, the circuit blocks away, the digital display module, the campus module, voice timekeeping module, industrial control modules
VerilogHDL
- vhdl多功能数字钟数字钟是一种用数字电路技术实现时、分、秒计时的装置,与机械式时钟相比具有更高的准确性和直观性-vhdl multifunction digital clock digital clock is a digital circuit technology with the hours, minutes, seconds, timing devices, and mechanical clock higher than the accuracy and intuitive
pmuxxplusii-vr
- 用VHDL开发的数字时时钟,可变宽度脉冲产生器 -VHDL development of digital clock, variable-width pulse generator
Usegg7_11s
- 用VHDL描述一个让6个数码管同时显示出来的控制器,同时显示出来0、1、2、3、4、5这6个不不同的数字图形到6个数码管上,输入时钟调节频率,使的能够观察到稳定显示出来的6个数字。可异步复位 -With VHDL descr iption of a let six digital tube display controller, 0,1,2,3,4,5 six different digital graphics displayed to six digital tube, adjust t
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
EDA_VHDL_shuzizhong
- EDA课程设计实验VHDL硬件描述语言实现数字时钟-EDA curriculum design experiments VHDL hardware descr iption language digital clock
time-project
- 用VHDL语言实现数字时钟显示、控制、复位、加减、按键消抖-Using VHDL digital clock display, control, reset, subtraction, key debounce etc.
VHDL
- 数字时钟,实现24小时数码管显示,可以实现按键校时-Digital clock, 24 hours to achieve digital display, you can achieve the key school
shuzhishizhong
- 数字时钟的verilog程序,课程设计,数字电子技术实验,VHDL-VHDL Verilog.
kebenchengxu
- VHDL代码,一些课本的小程序。包含3线-8线译码器,4选1选择器,6层电梯,8线-3线编码器,8线-3线优先编码器,8选1,BCD-7段显示译码器真值表,半加器,摩尔状态机,数字频率计,数字时钟,同步计数器,序列检测器的设计,序列信号发生器,一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
数字时钟
- 基于VHDL语言编写的数字时钟程序,经验证,可以用硬件实现(Based on VHDL language digital clock program, verified, you can use hardware to achieve.)