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经过验证的DW8051源码
- Synopsys开发，主频100M以上
经过验证的DW8051源码
- Synopsys开发的高速8051 IP core，已在coretools工具下验证。
Synopsys_8051
- MCU_8051的Synopsys，到现在，我还没有用过-MCU_8051 of Synopsys, until now, I have not used
Advanced.ASIC.Chip.Synthesis.Using.Synopsys.Design
- 使用synopsys design compiler和 prime time进行Asic开发的英文pdf-Advanced.ASIC.Chip.Synthesis.Using.Synopsys.Design.Compiler.Physical.Compiler.And.Primetime
StaticTimingAnalysis
- 静态时序分析（Static Timing Analysis简称STA）经由完整的分析方式判断IC是否能够在使用者的时序环境下正常工作，对确保IC质量之课题，提供一个不错的解决方案。然而，对于许多IC设计者而言，STA是个既熟悉却又陌生的名词。本文将力求以简单叙述及图例说明的方式，对STA的基础概念及其在IC设计流程中的应用做详尽的介绍。-Static timing analysis (Static Timing Analysis referred to as STA) through a com
vmm-1.0.1
- vmm-1.0.1.rar synopsys vmm systemverilog code-vmm-1.0.1.rar synopsys vmm systemverilog code
synopsys_VCS_TOOL_flow
- this pdf file will gives the details of synopsys tool design space and verilog HDL ASIC design based tips.also this pdf is a power point presentation with functional verification tool of synopsys VCS tool.... VERY USEFULL FOR PROFESSORS
DClicense_Install_crack_tool
- synopsys 公司Design compiler的安装步骤及license生成工具-Installation of the Design compiler,Synopsys and the neccesary tools for license crack and generate
hspice_models_quickref
- The Synopsys Discrete Device Library is a set of models of discrete components for use with HSPICE and Star-SimXT circuit simulators. It includes Diodes, FETs, MACROs (op-amps and comparators), Burr Brown, PMI, Signetics, and TI.
Mdiaanjiio
- 电机驱动driver电路 提供了H桥电路设计的几点思 -Motor drive circuit driver providess a H bridge circuit design Synopsys
ICC_scripts_official_flow
- 数字芯片设计后端 synopsys icc工具的官方流程脚本-scr ipts of official flow for IC compiler digital back-end design
lab2_synopsys_dc
- ECE 128 – Synopsys Tutorial: Using the Design Compiler Objectives: Synthesize a “structural” 1-bit full adder using the Synopsys Design Compiler Synthesize a “behavioral” 1-bit full adder using the Synopsys Design Compiler
designware_i2s
- ALSA SoC Synopsys I2S Audio Layer.
hspice
- Synopsys Hspice code for nand gate characteristics and five coupled lines delay calculation using w-element method
dc
- 使用synopsys的DESIGN COMPILER逻辑综合工具，流程通用脚本-the scr ipts of DESIGN COMPILER for synthesis
Synopsys_Sentaurus_Process_Diode.tar
- Synopsys Sentaurus Process Diode model
Or1200_cpu_scripts
- OpenRisc Synopsys Synthesis
or1200_DCReportsAndScripts.tar
- OpenRisc Synopsys Reports and scr ipts