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cpu的VERILOG描述
- RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL descr iption
simplecpu
- 一个16位简单CPU的Verilog源代码。
CPU_interface_verilog_code
- 包括一个基本的CPU接口的verilog程序及激励程序。
mips_project
- 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
RISC_8.rar
- 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。,Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
risc
- 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
S7_PS2_RS232
- 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
CPU
- verilog 实现的CPU，用Modelsim SE 6.2b 创建的工程，包含测试文件。- CPU of verilog implementation
071221088
- 实现一个简单的单周期流水线CPU，使用verilog语言开发 在quartus平台下运行-Implement a simple single-cycle pipelined CPU, using verilog language development platform running in quartus
061110061
- 在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令-Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions
cpu8
- 用Verilog仿真8条基本指令的CPU，是学习编写多条指令CPU的基础-Verilog simulation with the basic instructions 8 CPU, CPU to learn the basis for the preparation of multiple instructions
Tomasulo2
- 用verilog编写流水CPU。采用Tomasulo算法，进一步的减少了等式右边的各项暂停时间，并通过阅读文献，实现了一种基于此算法原理的机器PowerPC 620的CPU的雏形-Tomasulo Based Speculative Processor
single-clock-CPU
- 单时钟周期CPU，verilog语言编写，quartusII运行-A single clock cycle CPU
CPU
- 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
pipelined-CPU
- verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
88RISC-CPU
- cpu设计能在quartus上运行 用verilog语言-a cpu program use verilog on quartus
CPU(4)
- 基于ISE XILINX14.7开发的单周期CPU的基础指令实现代码 VERILOG-VERILOG implementation code base based on single-cycle instruction CPU ISE XILINX14.7 development of
CPU
- 语言为verilog，平台是ISE，指令较少。32位MIPScpu，可以直接运行(The language is Verilog, the platform is ISE, and the instructions are fewer. 32 bit MIPScpu, can run directly)