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verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
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SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
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a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
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Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
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verilog编写的异步fifo源代码，asyn_fiifo.v为顶层，调用其他四个文件，
-verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
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Verilog HDL code for synchronous SRAM FIFO
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