搜索资源列表
audio_aic23
- 数字音频实验测试工程,程序演示了通过I2C 总线对 TLV320AIC23 芯片的控制,各种音频环路,多种采样频率,DMA 音频采集和输出等 测试。程序中有详尽的说明。TLV320AIC23 的控制HDL模块Freedev_aic23 的7 号 寄存器提供了读和写两个端口,分别连接到数字音频芯片的AD 和DA 通道,每次可 读出和写入一个32 位宽的数据,分别是16 位左声道和16 位右声道的采样值。每 次数据就是一次采样的结果。如果是48K 采样率,那么每个数据时间间隔就是
PCBjq
- PCB环路设计技巧,关于PCB板级联、电源地管理、耦合处理、布局布线,有具体比较示例。
pll
- 该程序实现的锁相环,运行环境为matlab,二阶的环路滤波器
DIGTAL_FIR
- 环路滤波器的设计,基于FPGA的锁相环应用。
myDPll
- 本人写的数字锁相环,有模拟数据,学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。
D20CPUTEST
- 通过环路串口判断串行通信电平转换芯片功能是否正常,并通过读写DRAM 判断硬件。
环路检测器C51程序
- 环路检测器主要用于车辆检测及金属探测系统,这段小程序采用动态参数修*,纠正了以往固定参数法因积累误差导致的灵敏度随运行时间而降低,甚至死机的情况,此段程序已运行在设备中从未出现异常。
costas的verilog程序
- costas的verilog程序,包含乘法器,DDS,鉴相器,环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
gps_tracking
- 澳大利亚新南威尔士大学研究的GPS接收机的FPGA跟踪模块的.v程序,包括载波跟踪环路、码跟踪环路、通道累加等模块。-The University of New South Wales, Australia, the study of the FPGA tracking GPS receiver module. V procedures, including the carrier tracking loop, code tracking loop, the channel accumulati
dpll
- 基于Verilog的数字锁相环。包括三个模块,数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
loop
- 对锁相环路的仿真,二阶环的仿真与分析都可以通过这个文件来到完成-Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比,DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of
nfenpin
- N分频器则是一个简单的除N 计数器。分频器对脉冲加减电路的输出脉冲再进行N分频,得到整个环路的输出信号Fout。-N divider is a simple addition to N counter. Addition and subtraction of the pulse divider circuit output pulse frequency N again, the whole loop of the output signal Fout.
FPGAphaselockedloopdesign
- 介绍了应用VHDL技术设计嵌入式全数字锁相环路的方法,详细叙述了其工作原理和设计思想,并用可编程逻辑器件FPGA实现。-Introduce the application of VHDL technical design embedded DPLL road approach, described in detail its working principle and design idea, and programmable logic device FPGA implementation.
phase-locked
- 主要是关于锁相环的环路滤波设计与计算,非常经典的-Mainly on the phase-locked loop filter design and calculation, very classic
Interlooptestingbulkendpoint
- 批量端点间环路测试,用KEIL编写,适用于CY7C68013学习板的测试和开发-Inter-loop testing bulk endpoint, using KEIL prepared for the test board CY7C68013 learning and development
myd1loop
- dm642图像采集显示环路实验,在dm642开发平台上运行通过-dm642 image acquisition shows the loop experiment, in the dm642 development platform to run through the
Tcpip_loopback
- dm642 tcp/ip协议开发,数据发收环路,在dm642平台上运行通过-dm642 tcp/ip protocol development, data issued closed-loop, in the dm642 platforms through
lgmFramework
- dm642 tcp/ip协议开发,数据发收环路,在dm642平台上运行通过-dm642 tcp/ip protocol development, data issued closed-loop, in the dm642 platforms through
Low-phase-noise
- 能够完成低相噪、低杂波数字锁相环路滤波器-Low phase noise, low clutter digital phase-locked loop filter design