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uart.rar
- VHDL语言编写的全功能串口模块（包含DTR，RTS等管脚），在CPLD器件上测试通过,VHDL language, full-featured serial modules (including DTR, RTS pin, etc.), in the CPLD device test
uart.zip
- uart串口通信程序，用状态机实现的；测试通过，并且实践过,uart
uart.rar
- Verilog编写的UART程序源代码。测试成功。支持字符串发送,UART prepared Verilog source code. Successful test. Support string sent
uart
- uart的vhdl实现，包含完整quartus工程文件，相信会有较大帮助-uart vhdl quartus
UART
- 自己实用Verilog编写的UART程序，1位开始位，8位数据位，1位停止位，本测试程序配置完管脚后，实用串口大师发送数据，则返回数据为发送数据+1-Verilog prepared their own UART practical procedures to start a bit, 8 data bits, 1 stop bit, the test procedure End pin configuration, the utility serial Master to send data,
UART
- 这是VHDL编写的UART源码，测试成功，欢饮下载-It is written in UART VHDL source code, the test is successful, Huanyin download
UART
- 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
uart
- 用VHDL实现的一个uart控制器，输入时钟为33M-Use VHDL to achieve a UART controller, input clock for the 33M
UART
- 基于FPGA的UART实现 用VHDL编程-The UART-based FPGA using VHDL Programming
mini-uart
- Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
UART.ZIP
- 一个完整的用cpld实现串口功能的代码。经过验证，不经过任何修改便可使用。-serial port realized by vhdl.It has been tested and can be used with any change.
UART(FPGA)
- 基于现场可编程逻辑器件（FPGA）使用VHDL语言QuartusII实现UART通讯-Based on field programmable logic device (FPGA) using VHDL language QuartusII achieve UART communications
uart
- 基于FPGA的多调制UART的设计，相当不错，可估参考-FPGA-based multi-modem UART design, very good reference to assess
UART
- 包含一个在QUARYUS环境下运行的UART的工程，实际在EP2C20Q240上调试成功的通用串口VHDL程序-The QUARYUS environment contains a UART to run the project, the actual success of the EP2C20Q240 Universal Serial debugging VHDL programs
uart-vhdl-testbench
- simple uart vhdl behavioural model (package) vhdl testbench example
UART
- 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
uart
- uart接口读写控制器，已经在fpga上测试通过-uart interface to read and write controller, has been tested by fpga
uart
- FPGA中的UART模块，调试通过的哦！！希望对大家有所帮助，呵呵。。。我用的是quartus7.2版本编写的，当然也有些copy网上的-FPGA in the UART modules, debugging through the Oh! ! We want to help, Hehe. . . I use the quartus7.2 version of the written, of course, also some copy online
uart
- UART design with bist capability
uart-(VHDL)
- 利用VHDL语言实现的UART串口通讯，以经过下载验证-the UART program with VHDL as develop language