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codeofvhdl2006
- 【经典设计】VHDL源代码下载～～ 其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】 基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】
array_multiplier
- 4X4阵列乘法器，图可以按程序画看看，可以改进-4X4 array multiplier, see Figure can draw according to the procedure can improve
ILX509_7064
- 本文件是用CPLD（EPM7064）驱动线阵CCD（ILX509），其中包括原理图和程序-This document is a CPLD (EPM7064) driver line array CCD (ILX509), including schematics and procedures
SOC_CCD
- 基于SOC 的线阵CCD 图像采集单元设计，关于ccd的资源-SOC based on the linear array CCD image acquisition unit design resources on the ccd
CPLDforCCD
- 基于CPLD的光积分时间可调线阵CCD驱动电路设计-CPLD-based optical integration time adjustable linear array CCD Drive Circuit Design
FPGA_signal_general
- 摘 要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。 关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are giv
REACH
- 基于VHDL的异步串行通信电路设计 随着电子技术的发展，现场可编程门阵列FPGA和复杂可编程逻辑器件CPLD的出现，使得电子系统的设计者利用与器件相应的电子CAD软件，在实验室里就可以设计自己的专用集成电路ASIC器件。这种可编程ASIC不仅使设计的产品-VHDL-based asynchronous serial communication circuit design with the advent of electronic technology, field programmable g
Multiplier
- 用VHDL语言描述的几个乘法器实例，如串行阵列乘法器等-VHDL language used to describe a few examples of multipliers, such as array multipliers, such as serial
FPGA_NEW_APPROACH_TO_IMPLEMENT_CHAOTIC_GENERATOR.
- In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the freq
Pseudo-Random_Bit_Sequence_Generator_by_FPGA
- A spatiotemporal chaotic map is digitized to develop a highly paralleled PRBS generator that accommodates to FPGA (Field Programmable Gate Array) implementation in present paper.
Hardware_Speedup_DSP_FPGA
- 现场可编程门阵列（FPGA）已经不再单纯应用在芯片与系统之间的直接互联层，在软件无线电（SDR）中，FPGA逐渐用做通用运算架构来实现硬件加速单元，在降低成本和功耗的基础上提升性能表现。SDR调制解调器的典型实现包括通用处理器（GPP）、数字信号处理器（DSP）和FPGA。而且，FPGA架构可以结合专用硬件加速单元，用来卸载GPP或DSP。软核微处理器可以结合定制逻辑，扩展其内核，也可以将分立的硬件加速协处理器添加到系统中。此外，还可将通用布线资源放在FPGA中，这些硬件加速单元可以并行运行，进
Libero8.5_UG
- Libero集成设计环境(IDE)8.5版本，这套完整的软件设计工具系列已进一步扩展，支持新近推出的nano版本IGLOO和ProASIC3现场可编程门阵列(FPGA)。-Libero Integrated Design Environment (IDE) 8.5 version, this complete series of software design tools have been further expanded to support the recently introduced
FPGA_design_part1
- FPGA是英文Field Programmable Gate Array的缩写，即现场可编程门阵列，它是在PAL、GAL、EPLD等可编程器件的基础上进一步发展的产物。-FPGA is the English acronym for Field Programmable Gate Array, or field programmable gate arrays, it is in PAL, GAL, EPLD and other programmable devices based on the
LPC2DDR2
- Module Function Descr iption: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the
8QAM
- 8 array QAM design using HDL
TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA
- Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bay
dianzhen
- FPGA嵌入式开发的源代码，本实例是实现点阵的通信-implementation of pointer array
array-multiplier
- source code for array multiplier
Array-multiplier
- Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
array-led-display-chinese-characters
- 基于fpga驱动点阵显示汉字，4*4点阵，采用Verilog-array led display chinese characters