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200512251221612004
- 本文件是altera公司fpga的ip核,从国外网站下载的免费源码。-ALTERA This document is the company they simply ip nuclear, downloaded from the web free source.
cpld
- This file is gotten from the web.
dram
- 4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.
petalogic.rar
- 这个是一个基于Xilinx FPGA的微控制器软和microblaze移植uclinux的说明文档。由于这些文件都是以网页的形式存在的,所以我下来组织成了电子书的格式,方便大家查看。并且希望对那些希望在FPGA上做嵌入式开发的人有所帮助。还有,上面的东西都是从petalogic的网站上下载的,版权归petalogic所有,我只是把它介绍给大家。,This is a Xilinx FPGA-based soft MCU microblaze documentation of uclinux tra
xapp687
- xapp687 code from xilinx web down load new-xapp687 vhdl from xilinx web
recuart_50m
- 本代码功能为实现接收PC发送的串口数据功能 程序通过quartusII 8.1编译,使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 (开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) 有需要的朋友可以下载参考-The code functions to achieve the receivi
BusMasteringPCIExpressInAnFPGA
- This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex pr
web
- 模拟网络串行通信 近期对计算机间通信比较感兴趣,同时研究usb通信原理,起步为串行通信于是想为更好地理解其机理做一定基础性研究,故做了异步串行通信设计实验。 经过QUARTUS验证,获得了一等奖!-Simulation of the recent serial communication network between the communication of more interested in computers, communications usb at the same time
PWM_VerilogHDL
- altera公司网站上的详细的PWM设计的Verilog hdl源程序,大多数都采用这个-altera company' s Web site the detailed design of the PWM source Verilog hdl, most have adopted this
oc_i2c_master
- I 2 C 是两线双向的串行接口,非常适合芯片级的通讯。由于 SOPC Builder并未提供 I 2 C 内核, 本节所描述的 I 2 C 内核是 Richard Herveille 制作的并发布到网上去的免费核。 关于 I 2 C 核的使用方法,请见光盘中 oc_i2c_master文件夹下的使用说明.txt。 -I 2 C is a 2-line bidirectional serial interface, very suitable for ch
vhdl_serial_receiver
- a good serial receiver in vhdl , there is also transmitter code along with this , check it in same web
VGA_test50m
- 本代码功能为实现VGA显示功能,即实现在显示器上显示640*480彩条。 程序通过quartusII 8.1编译,使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 (开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) 有需要的朋友可以下载参考-The code functions to achi
IR
- 本代码功能为实现38/30KHZ红外线接收功能 程序通过quartusII 8.1编译,使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 (开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) 有需要的朋友可以下载参考-The code functions to achieve 38/30KHZ
ps2test
- 本代码功能为实现接收PS2键盘编码功能。 程序通过quartusII 8.1编译,使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 (开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) 有需要的朋友可以下载参考-The code functions to achieve the receiver
halfclk
- 本代码功能为实现输入时钟的1.5分频功能。 程序通过quartusII 8.1编译,使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 (开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) 有需要的朋友可以下载参考-The code functions as the input clock fre
CamWizard_install
- cam project on fpga, web cam controller
RVD.tar
- Realtime Video Display - Displaying real time video captured from a camera is an essential function in a vari- ety of applications ranging from CCTV se- curity monitoring to webconference meet- ings. In this project, we propose to build a s
DE2_Web_Server
- 此文件是altera公司发布的基于DE2开发板的-web例程,能实现DE2开发板与计算机之间的信息传输,采用vhdL语言编写。-This file is Announces altera DE2 development board based on the-web routine, to achieve DE2 development board and the transfer of information between computers, using vhdL language.
my_kmp_matching
- KMP算法的Verilog HDL实现,模式串从模块的外部输入,计算next函数,然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。-Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment
vgacode
- VGA彩条信号发生器,从网上搜到的,希望对大家有用-VGA color bar generator, search the web, and we hope to be useful