pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies

AT89C2051+MC44817锁相环电路CATV射频调制器汇编源代码。-AT89C2051+ MC44817 PLL circuit CATV RF modulators compiled source code.

采用集成化（包括VCO PLL LPF）的锁相环进行点频信号发生的的源代码-The use of integrated (including VCO PLL LPF) for the phase-locked loop frequency signal occurred at the source code

verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in

PLL350锁相环源码，设置频率、分频比等等其他功能-PLL350 PLL source, set the frequency division ratio, etc. Other features