搜索资源列表
nguyenvanduan_group4_TC304
- ASM chart for altera de1
DE1lab1
- DE1 altera VHDL lab 1 exercise
DE1lab2
- DE1 lab2 altera Vhdl
as1
- Verilong HDL是最frequenctly使用的硬件描述语言，因为它的简单和方便的属性之一。这当然AIMES设计一个数字时钟，配备4段显示，秒表和时间设定使用这种语言，甚至一些额外的功能，fundamatal。 DE1板设计时钟的实施贡献-Verilong HDL is one of the most frequenctly used hardware descr iption language because of its simple and convenient propertie
DE1_Default
- this the default setting for DE1 board that will reprogram the board to the default setting-this is the default setting for DE1 board that will reprogram the board to the default setting
DE1_SOC_ADC_test
- DE1中ADC Converter (AD7982)的值 可顯示在七段顯示器上-DE1 value in ADC Converter (AD7982) can be displayed on the seven-segment display
SDRAM-and-FIFO-for-DE1-SoC-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.