搜索资源列表
VGA 256灰阶的显示
- VGA 256灰阶的显示VGA 256灰阶的显示VGA 256灰阶的显示
分频器
- 通用分频器 +仿真
Verilog数字系统设计教程(第2版)
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed o
QuickSOPC-1C6
- VHDL实验版。供大开发的所有程序。家学习交流！-VHDL experimental version. For the development of all programs. Home Learning Exchange!
FIFO_SRAM
- 可用于FIFO功能的SRAM读写器.....绝对好用-SRAM FIFO function can be used ..... definitely helps the reader ...
Experiment02
- FPGA低级建模试验二流水灯加闪烁等，通过板级调试-FPGA test two low-level flow modeling lamp, flash, etc., by board-level debugging
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
seg7_lut_8_0.rar
- 七段阴极数码管的FPGA控制程序，开发平台为ISE或者quartus,Seven-Segment LED cathode the FPGA control procedures, development platform for the ISE or Quartus
flash02
- 一个我自己写的FPGA读写FLASH代码，在QUARTUS 下用verilog编写，falsh的型号是k9f5608u0d,经测试可以用。-I wrote a FLASH FPGA to read and write code, written in QUARTUS next with verilog, falsh model is k9f5608u0d, can be tested.
cic512.rar
- 5阶cic滤波器，抽取12倍，的verilog程序，已经通过仿真验证，一、具有很高的速率,5-order CIC filter, collected 12 times the Verilog procedures are by simulation, one with a very high rate
speech
- 用verilog HDL实现自相关算法！ RTL级可综合代码！ 通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
RS(255-233)decode
- 基于verilog HDL RS(255,223)的编译器源代码-Based on verilog HDL RS (255,223) of the compiler source code
encode
- 用verilog写的8B10B编码源代码。似乎有点难度来理解。这里并未使用case语句，而是完全的用的组合逻辑化简-Use verilog write 8B10B encoding source code. Seems difficulty understood.
code
- 《无线通信FPGA设计》书里的matlab和verilog代码-the matlab and verilog code in 《Wireless Communications FPGA design》
IIR_Filter_8
- verilog实现8阶的iir滤波器。对于刚学习verilog的朋友来说是一个易懂的学习资料。-verilog order to achieve the iir filter 8. For just learning verilog friend is a easy to understand learning materials.
key_interface
- verilog写的程序，是带按键消抖程序。。对于新手具有参考-verilog write the program, with key debounce program. . A reference for the novice
AD7864
- 这是对上次AD7864采样程序的改进，增加了FIFO的编程，功能比上次源码更加完善！-This sourse is modified and I have added the program of FIFO,so its function is better then privious one.I hope it is helpful for you!
FM0_encode
- 详细介绍了FM0编码，采用verilog编码语言-FM0 encoding, using verilog
yibu_FIFO_design
- 异步FIFO实例，精通verilog hdl中的例子，供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning
clock
- EDA 数字钟实现文件 能够实现计时,闹钟,校时功能 -EDA digital clock time to achieve the realization of paper, alarm clock, school functions