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frequency-synthesis
- 常用锁相环芯片参数,功能,使用环境。频率合成发展的历史及前景-Common PLL chip parameters, function, use of the environment. To frequency synthesis history of the development and prospects
make-PLL-with-matlab
- 用matlab仿真锁相环 来实现载波同步,调频等功能-Use Matlab simulation phase-locked loop to achieve carrier synchronization, FM
low-jitter-Clock-IC
- 每个数码系统之所以正常准确工作的基础是其心脏 – 时钟序列的无误. 而用来产生时钟信号的资源有许多种: 系统主芯片输出时钟信号, 以MCU微处理器来产生时钟, 以成本较低的晶振来产生时钟信号, 但是还是有很多人不知道或不了解我们还有另外一个选择:用一个集成电路PPL(锁相环)时钟芯片.-Each of the digital system is the reason why the normal work accurately based on the its heart- clock sequ
Direct-Digital-Synthesis
- 频率合成经典文档,锁相环的知识,杂散 以及消除方法-Direct Digital Synthesis
ReaserchOf2MWDFIGSystem
- 在2 MW 双馈风电变流器的开发过程中,电磁暂态仿真是验证控制策略和制定相关技术参数的重要手段。建立 了2 MW 双馈风力发电系统电磁暂态仿真模型,介绍了电压空间矢量脉宽调制(SVPWM)技术在PSCAD/EMTDC 的 实现方法,真实反映了变流器的动态开关过程和谐波特性。另对网侧变流器的软件锁相环(SPLL)进行了优化设计, 使之能快速、准确地跟踪电网基波正序电压,有助于改善网侧变流器在电网不对称故障期间的动态控制性能。-2 MW doubly-fed wind power con
NE564D
- 基于NE564D锁相环频率合成器的设计,毕业设计来的-Based NE564D PLL frequency synthesizer design, graduate design come
DS-01444A
- 光伏微网逆变器设计手册,从光伏板特性分析到DCDC反激升压再到DCAC逆变最后到锁相环检测并网都详细说明。-PV micro-inverter design manual, from the characteristics of photovoltaic panels to boost DCDC flyback DCAC inverter then finally to the phase-locked loop detection and network are described in de
ADPLL-patent
- 全数字锁相环的几个专利,全部为英文,很好的参考资料-DPLL patent
pll-matlab
- 通信系统锁相环pll matlab仿真,基于微分方程的一阶、二阶锁相环-Phase-locked loop pll matlab communication system simulation, based on first-order differential equations, second-order phase-locked loop
Phase-Locked-Loop-FAQ
- 关于锁相环设计经常遇到的一些问题的官方解答.为设计者提供一些参考.-PLL design on some of the problems often encountered in the official answer. Provide some reference for the designer.
qpsk-carrier-pick-out
- QPSK基带数字相干解调的载波提取_陈教芳 本文介绍了基带数字相干解调的载波恢复锁相环的结构原理,并对其进行了性能分 析.与四倍频方法比较,在相同条件下,前者比后者环路信噪比高5一1odB.实验结果表 明,恢复的载波稳定性良好。 -qpsk carrier pick out
aaa
- 一种全数字时钟数据恢复电路的设计与实现,提出一种改进型超前滞后锁相环法的全数字时钟恢复算法,与同类电路比较,具有数据码率捕获范围宽、捕获时间短的优点。-Clock Date Recovery(CDR)circuit is a important part of data transmission equipment.For the burst data transmission,the traditional phase—lock loop can hardly achieve the re
PLL
- 自己用PSCAD软件搭建的锁相环模型,大家多多交流讨论-PLL MODEL
The-principle-of-phase-locked-loop
- 主要介绍了锁相环的基本原理,PLL参数测试示例展示,重点分析了CD4046——通用的CMOS锁相环集成电路,MT8870——音调译码器(Tone Decoder)是MITEL 公司所开发生产为一颗常用复频译码IC。-Introduces the basic principles of phase-locked loop, PLL parameter test sample shows, analyzes the CD4046-- generic CMOS PLL IC, MT8870-- ton
Phase-Locked-Loop-PLL-lecturer
- 锁相环实验,PLL参数测试,锁相环PLL原理与应用,环路滤波器 -The experimental phase-locked loop, PLL parameter testing, and application of the principle of the PLL loop filter
PLL_theta
- PLL锁相环的角度生成问题,角度的代入运算前的修正问题,总算是解决了!-PLL PLL angle generation problem, the angle of substitution before the operation to fix the problem, finally solved!
PLL0
- PLL锁相环运用在矢量变换中的matlab的仿真模型,试试看咯!-PLL is used in the vector transformation of matlab simulation model, try slightly!
suoxianghuan
- 锁相环相关知识,包含二阶 三阶 锁相环的介绍以及编程实例汇总-Phase-locked-related knowledge, presentation and programming examples included 2nd and 3rd order PLL summary
digital-PLL
- 收集的关于数字锁相环的理论模型和分析讨论,适用于FPGA的数字电路设计。-Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.
74hc4046
- 本设计根据锁相环原理,通过两片CD4046搭接基本电路来实现FM调制/解调电路的设计,将调制电路的输出信号作为解调电路的输入信号,最终实现信号的调制解调。原理分析,我们得到的载波信号的电压 大于3V,最大频率偏移 5KHz,解调电路输出的FM调制信号的电压 大于200mV可以看出我们的具体设计符合设计指-The design phase locked loop principle, by two overlapping basic circuit to achieve CD4046 FM mod