搜索资源列表
space-phase-modulation-based-on-8-bit-microprocess
- 这是基于78k0八位微控制器的空间相位调制技术介绍以及主体程序-78k0 which is based on 8-bit microcontroller space phase modulation technology presentations and the main procedure
SOA Cloth Simulation with 256-bit Intel Advanced Vector Extensions (Intel AVX)
- This article describes a code sample that uses the Intel® Advanced Vector Extensions (Intel® AVX) for computing mesh-based cloth simulation. A structure of arrays (SOA) implementation is used to maximize data parallelism enabling the usage of 256-bit
BIT虚拟仪器设计与实验作业
- 本资料为BIT虚拟仪器设计与实验课程提供参考
BICM8PSK
- bit-interleaved coded modulation (BICM-ID) with 8psk
multi_wavelet
- multi_wavelet An Image Digital Watermarking Algorithm Based on Bit-Plane-Decomposition and Multi-Resolution-Decomposition -multi_waveletAn Image Digital Watermarking Algorithm Based on Bit-Plane-Decomposition and Multi-Resolution-Decompositi
fpgafft
- :文章针对目前数字信号处理中大量采用的快速傅立叶变换[FFT] 算法采用软件编程来处理的应用现状,在对FFT 算法进行 分析的基础上,给出了用FPGA[Field Programmable Gate Array] 实现的8 点32 位FFT 处理器方案,并得到了系统的仿真结果。 最后在Altera 公司FLEX10K系列FPGA 芯片上成功地实现了综合。-Based on the analysis of the FFT algorithm , a reasonable logic str
ber
- Bit error probability curve for QPSK mimo 1*2, Bit error probability curve for QPSK mimo 1*4-Bit error probability curve for QPSK mimo 1*2, Bit error probability curve for QPSK mimo 1*4
QPSK
- 提出了一个采用(2,1,7)卷积码+QPSK的中频调制解调方案,并在Xilinx公司的100万 门FPGA芯片上实现了该系统。该系统在信噪比SNR为6dB左右时可实现速率超过1Mbit/s、误码率 小于10-5的数据传输。 -Proposed a use of (2,1,7) convolutional code+ QPSK modulation and demodulation of the IF program, and in Xilinx' s FPGA chip one
ber
- bit Error Rate in Wireless communication
bit-error-rate_simulation_using_matlab
- Bit-Error-Rate Simulation Using Matlab
8-bit-alu
- this is an 8 bit alu. to perform various arithmetic and logical operations
CRC
- 本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8 位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并 行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating differ
AD9763
- ad9763 10-Bit, 125 MSPS Dual TxDAC+, high performance analog to digital converter from AD.
product_final
- program for multiplication of two 4 bit binary numbers... If you have any doubt,then mail me at prem_bombay@yahoo.co.in -program for multiplication of two 4 bit binary numbers... If you have any doubt,then mail me at prem_bombay@yahoo.co.in
ALU
- Write an 8085 ALP to design a 4-bit ALU. The ALU should be able to perform addition, subtraction, AND operation, OR operation on 4-bit inputs based on the desired operation
synchronization
- 各种同步实验及系统设计。包括：同步载波提取、帧同步信号提取实验、位同步信号提取实验以及衰落信道帧同步电路设计与实现和位同步的提取方法设计。-Various synchronization experiment and system design. Including: synchronous carrier extraction, frame synchronization signal extraction experiments, bit synchronization signal ext
Low-Bit-Rate-Speech-Coding
- Low Bit Rate Speech Coding-- master degr-Low Bit Rate Speech Coding master degree
chapter2-low-bit-rate-speech-coding
- Chapter 2 Low Bit-Rate Speech Coding In this chapter an overview is given of speech coding techniques at several bit rates. Most of them use Linear Prediction. This overview is not meant to be complete its purpose is to make the reader somewhat
4-bit-multiplier
- 4 bit multiplier program using shift and multiply
64-Bit comparator
- 64-bit comparator using different logic designs