搜索资源列表
ram_sp_sr_sw
- ROM using file.suite in design a simple CPU
ram_dp_sr_sw
- suite in design a simple CPU
cam
- Desin 1 simple CPU. important module
GPIO
- GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interface-Use verilog to design a 48 control points that can be programmed to input or output controller
led_test1
- 在de2板上的led流水灯显示 C语言实现 实验环境Quartus2+nios2-De2 board in the water led light shows C language environment for the realization of the experiment Quartus2+ nios2
eth_txethmac
- It is a ieee 802.3 transmitter module-It is a ieee 802.3 transmitter module
display
- 这是一个给予FPGA的动态显示代码，是利用verilogHDL实现的-It is a dynamic display of the FPGA code, the use of verilogHDL to achieve the
Lab1
- My first project written in Quartus II by using VHDL, executed some tasks that display word on 7-segments LED through the simulated 5-to-1 multiplexer. My code is easy to acquire and may be help usefull.
chengfa
- 用VerilogHDL的16*16乘法器的设计实现，采用的是移位相乘方法-VerilogHDL with 16* 16 multiplier design using the method of displacement multiplied
61EDA_D1049
- 频率计设计６位数码管还是拉倒机是大撒但是的撒但是 -6 Cymometer design digital control machine or leave it is spreading
jc2_ver
- Johnson counter with verilog
watchver
- watchdog with verilog
75448152Project1-DDS
- 利用DDS芯片实现正弦波输出 使用synplify pro建立工程，加入这些文件 编译后生成.vqm的文件 用quartusII打开.vqm文件，编译通过 加入.vwf波形仿真文件，进行波形仿真 最后分配引脚，下载即可 - realization of sin wave in FPGA
serial1
- 串口简化verilog模型，固定波特率4.8k, 输入、输出使能输出-Verilog model of serial simplified
i2c_verilog
- verilog i2c 控制源代码，包括读写控制-verilog i2c source code control
cordic
- its all about cordicits all about cordic its all about cordicits all about cordic
segment
- 7 segment display using verilog interfacing fpga and 7 segment display
watchvhd
- for vhdl code to program and testing the gates
pong
- software testing code and debugging using vhdl
viterbi_decode
- 本程序为V_log代码，实现维特比译码，卷积码为（2，1，3）-viterbi_decode (2,1,3)