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VerilogHDLshejifengpingqihe32weijishuqi
- 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
VerilogHDL
- verilog 手册初学者的一个非常好的学习资料
display
- 这是一个给予FPGA的动态显示代码，是利用verilogHDL实现的-It is a dynamic display of the FPGA code, the use of verilogHDL to achieve the
chengfa
- 用VerilogHDL的16*16乘法器的设计实现，采用的是移位相乘方法-VerilogHDL with 16* 16 multiplier design using the method of displacement multiplied
PKUverilogPPt
- 北京大学VerilogHDL学习课件，很不错-Peking University VerilogHDL Learning Courseware
verilog-traffic-light
- 基于VerilogHDL设计的交通灯控制系统本设计利用Verilog HDL 语言、采用层次化混合输入方式,可控制4个路口的红、黄、绿、左转四盏信号灯,让其按特定的规律进行变化。 -This design using Verilog HDL language, adopt hierarchical mixed input method, four intersection control of red, yellow, green, left four lamp lights, let its
veriloghdl
- verilog HDL 实用教程 包含基础的概念和一些简单应用实例-the verilog HDL practical tutorial contains the concept and some simple application examples
verilogHDL
- 夏雨闻经典Verilog HDL详介绍了verilog HDL语法规范和无数经典例程，是和初学者学习，简单易懂。-Xia Yu Wen the classic Verilog HDL detailed introduction verilog HDL syntax specification and countless classic routines, and for beginners to learn, easy to understand.
VerilogHDL-for-timing-design
- 这是一本关于如何进行硬件时序设计的文档，对时序设计困难的朋友很有帮助 VerilogHDL时序篇.pdf-This ebook is about the timing design in FPGA, very helpful
CPU-implementation-in-verilog
- 用verilogHDL实现CPU各项功能-The implementation of CPU funtions based on verilogHDL
VerilogHDL-DDR2SDRAM
- 关于DDR2 控制器的设计 是通过verilog语言设计-DDR2 controller design through verilog language design
SharpVerilog-basic-guide
- verilogHDL基础知识手册，简明清晰介绍verilog基本用法，适合基础薄弱的新手。-Basics Guide verilogHDL, clear and concise introduction to the Verilog basic usage, suitable for weak foundation novice.
lab-2-Memery-design-with-VerilogHDL
- 用verilog 编写的32位存储器代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-32-bit memory code written in verilog, through modusim simulation, including the principle diagram and code, in the form of a lab report write
lab3controler-design-with-Verilog
- 用veriloghdl 编写的控制器代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-Controller code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
lab-4-cpu-design-with-Verilog-HDL
- 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
VerilogHDL-v5
- VerilogHDL那些事儿_建模篇v5-VerilogHDL those things _ Modeling articles v5
MOTOROLA-Verilog-HDL-Coding-standard
- 文档是关于verilogHDL的代码规范的，编写方是MOTOROLA，对于规范VerilogHDL格式有借鉴意义-Document is about verilogHDL code specification, the preparation side is MOTOROLA, VerilogHDL format for standardizing reference
fpga_programming_using_verilog_hdl_language_summe
- FPGA Programmingusing VerilogHDL Language
adder_sub_mul
- 加法器，减法器，乘法器，超前进位，一位拓展成四位-adder and subber are written by the language of VerilogHDL one bit to four bits.
VerilogHDL
- 这是verilog硬件描述语言的一些知识，比较全面。值得下载。-This is verilog hardware descr iption language, some knowledge, more comprehensive. Worth downloading.