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Booth_mutipler
- 布思基四乘法器实现,很好用,快来看,希望对大家有所帮助.-Busaiji four multiplier, useful, Come see, we want to help.
The Linux Kernel API
- The Linux Kernel API是学习linux编程必备资料，学会API那么做软件开发就会事半功倍。-The Linux Kernel API is learning linux programming required information, and learn to do it API software development will multiplier.
Adaptive-digital-filter
- 自适应数字滤波器中乘法器的硬件设计，用VHDL语言实现自适应数字滤波器。-Adaptive digital filter in multiplier hardware design, using VHDL language adaptive digital filter.
booth_multiplier
- Booth multiplier written in verilog
DDS-baseddesignofthesinusoidalsignalgenerator
- 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度， 由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the singl
FPGA
- 基于FPGA数字乘法器的设计：数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA 的数字乘法器．分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the use of digital signal processin
Coursework3
- This paper illustrates an approach to design a 4 Quadrant multiplier circuit using BJT. A Quadrant multiplier basically consist of 2 matched differential pair units with BJTs. This principle was established by B.Gilbert in 1968 and the circuit is kno
multi
- This a baugh-wooley multiplier verilog code-This is a baugh-wooley multiplier verilog code
doublemult
- 设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和 树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把 设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确 并对FPGA 实现的时序结果 进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm fo
4-bit-multiplier
- 4 bit multiplier program using shift and multiply
Multiplier
- 详细介绍了给予Verilog的乘法器设计过程。-Details the the multiplier given Verilog design process.
wallacetree-16bit-multiplier
- 这是一种多功能的乘法器的设计思路,只要有了它,就能快速的解决乘法的问题,是卷积,求和,积分的好帮手.-This is a versatile multiplier design ideas, as long as you have it, you can quickly solve the problem of multiplication, convolution, summation, integral a good helper.
Multiplier
- 乘法器课程报告，华莱士树算法硬件实现，讲解详细-Multiplier course reports, Wallace tree algorithm implemented in hardware
the-Lagrange-multiplier-method-
- 约束优化算法：拉格朗日乘子法matlab程序-Constrained optimization algorithm: the Lagrange multiplier method and matlab program
4bit-multiplier
- four bit multiplier for testing softwares
4bit-booth-multiplier
- four bit booth multiplier for testing software
Systolic-Multiplier
- Systolic multiplier is used to multiply 18-bit or more bit multiplication
verilog-code-for-8bit-multiplier-using-vedic-algo
- The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
Design-of-Fixed-Width-Multiplier-Using-Baugh-Wool
- Design of Fixed-Width Multiplier Using Baugh-Wooley Algorithm
multiplier
- structural multiplier