搜索资源列表
Execise
- altera官方网站上资料的示例代码Quartus II Software Design Series Foundation-altera official website information sample code Quartus II Software Design Series Foundation
FPGA_AD
- 基于Altera的FPGA开发的基于FPGA的AD转换功能，完全通过验证。-Altera s FPGA-based development of FPGA-based AD conversion function, fully validated.
flash_controller
- Altera下的FPGA运行Nios处理器的flash控制器-Altera
altera_maxII_PCI_Verilog
- Altera的MAXIICPLD模拟PCI接口的Verilog代码-Altera
15Altera_IP
- 里面包含15个altera的IP核的源代码,包括I2C，UART，VGA_SYN-Which contains 15 nuclear altera the IP source code, including I2C, UART, VGA_SYN
a_block_with_several_functions_with_Verilog_HDL.ra
- Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。 本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍，Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能
ofdm_modulation_v72
- 基于altera 芯片得ofdm调制解调源程序-Altera chips were based on OFDM modulation and demodulation source
HardwareUDP
- Hardware UDP, implementation of UDP based on Altera DE2 using Verilog
Avalon_VGA_Controller
- Vga Controller source code for Altera FPGA
fpga_div
- Altera的FPGA，设计的硬件除法器-Altera' s FPGA, the design of the hardware divider
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
my_ram_vhdl
- how to infer ram for fpga altera xilinx
PLLTEST
- Altera Quartus to Pll Source
EP1C6Q240C6
- EP1C6Q240C6开发板原理图，Altera公司的Cyclone系列FPGA—EP1C6Q240-EP1C6Q240C6 development board schematics, Altera' s Cyclone series FPGA-EP1C6Q240
DE2_pin_assignments
- altera DE2开发板的管脚配置文件很好用的哦-altera DE2 development board of the pin configuration files used by Oh well
EP1C6_EP1C12
- Altera FPGA Cyclone I EP1C6 EP1C12 最小系统 开发板 -the minimum system of Altera FPGA EP1C6 and or EP1C12
EP2C5
- Altera FPGA Cyclone II EP2C5 最小系统 开发板-the minimum system of Altera FPGA EP2C5 and or EP2C8
DE2_schematics
- Altera FPGA DE2的原理图,相信有很大的帮助,经典的FPGA设计电路及相关的接口都有了。-Altera FPGA DE2 the schematic diagram, I believe there is a great help, classic design FPGA circuits and related interfaces have.
miffile
- 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
Leon_tutorial_Altera_english
- Leon Altera Boarsds. This shows how to synthesis leon processor to altera boards through the use of quartus 3.-Leon on Altera Boarsds. This shows how to synthesis leon processor to altera boards through the use of quartus 3.