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Altera_timing
- 本文件讲述了Altera的FPGA的时序原理-This document describes Altera' s FPGA timing principle
Splitter
- Splitter file to be used to split altera avalon st video stream into two avalon st streams.
vga2
- VHDL code for UP2 board of Altera, that generate a video signal to VGA port.
SOPC_Nios
- Altera SOPC Builder 提供了 Nios Ⅱ处理器及一些常用外设接口 ,但并没有提供 12864 液晶模块的接口及驱动。-Altera SOPC Builder provides the Nios Ⅱ peripheral processor and a number of commonly used interface, but did not provide 12864 LCD module and the drive interface.
AlteraArticleContestPapers
- 本源码为Altera中国大学生电子设计文章竞赛的历届获奖论文汇编，内容主题涵盖如下4个方面： PLD在通讯、消费类、计算机和工业控制方面的应用 Altera器件、Quartus® II 软件的设计和优化技术 Altera FPGA在数字信号处理中的应用 Nios® II 软处理器在各领域的应用 获奖作品均是是参赛者独立设计的未曾公开发表过的原创性作品，在作品原创性和特色性 、实用性（结合当前的热点应用） 和作品
Altera_FPGA_pwm
- 基于FPGA（ALTERA公司的FPGA）PWM的测试程序。-Based on FPGA (ALTERA' s FPGA) PWM test procedures.
Altera_FPGA_motor
- 基于Altera的FPGA的开发板的PWM测试程序。板子是周立功的MagicSOPC的。-Altera' s FPGA-based development board of the PWM test procedure. Ligong week the board is the MagicSOPC.
FFTVHDl
- 基于FPGA的fft实现 摘要：本系统基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核，代替传统DSP芯片或高性能单片机，实现了基于FFT的音频信号分析。-FPGA-based realization of the fft Abstract: This system is based on Altera Cyclone II family of embedded high-performance FPGA embedded IP core
DE1_i2sound
- Altera的DE1平台资料，实现de1的音乐播放功能-Altera' s DE1 platform for information, the realization of the music player function de1
led
- 与串口通讯控制led（使用VHDL硬件描述语言，通过Altera QuartusII 开发）-Serial control and communications led (the use of VHDL hardware descr iption language, through the development of Altera QuartusII)
adsx
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
ad_pll
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
uart16450
- uart 16450合集,xilin altera lattice-collection of uart controller 16450
jtag_uart
- Configuration and usage of Altera s JTAG UART.
SRAM_Controller
- Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
DE2_NIOS_HOST_MOUSE_VGA
- 在ALTERA的DE2开发板上做的关于HOST_MOUSE的例子，基于Quartus II 和SOPC Builder以及Nios II IDE平台所完成！-ALTERA development in the DE2 board to do on HOST_MOUSE example, based on the Quartus II and SOPC Builder and Nios II IDE platform completed!
DE2_SD_Card_Audio
- 在ALTERA的DE2板子上做的一个读写SD卡的例子，基于QUARTUS II ,SOPC BUILDER ,Nios II IDE实现的，从SD卡读写东西-The DE2 board in ALTERA do an SD card reader example, based on the QUARTUS II, SOPC BUILDER, Nios II IDE achieved something from the SD card reader
fpga_tcl
- Altera FPGA的特殊管脚的连接(中文).doc TCL_教程.pdf-Altera FPGA tcl
modlesimcrack
- altera配套modelsim破解程序，绝对好用！注意要改环境变量-altera crack modelsim matching procedure, the absolute ease of use! Attention to environment variables to be changed
f_divider
- 16-bit frequency divider (32 MHz,16,8,...) based on altera fpga.