搜索资源列表
u26a_spice
- ddr2控制器一些源码，控制时序及怎样通过嵌入式cpu来进行控制的实例-ddr2 Controller some source code, and how to control the timing of embedded cpu passed to the control of the examples
OpenSPARC_DDR2_controller_RTL_
- 基于FPGA的DDR2控制程序，用verilog编写的。,FPGA-based DDR2 control procedures, prepared by using Verilog.
DSP-533M-ddr2RAM4C6455.rar
- C6455 的 533M DDR2 ram 控制程序。完整代码，可以直接使用。,533M DDR2 ram the C6455 control procedures. Integrity of the code, can be used directly.
c_xapp702
- V4系列FPGA控制DDR2器件的中文介绍-V4 Series FPGA device in Chinese control of DDR2 Introduction
sp601_MIG_rdf0005_12.2
- spartan—6fpga 用mig生成ddr2接口的ip核，用户可以直接调用此ip控制ddr2-spartan-6fpga generated by mig ddr2 interface ip core, the user can call this ip control ddr2
ssss
- spartan—3a对ddr2读写控制源程序，有verilog和vhdl版本-spartan-3a ddr2 read and write control of the source, there are versions of verilog and vhdl
ddr2_test
- 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
ddr2_demo
- lattice 操作DDR2控制器verilog源代码-the verilog source code of ddr2 control of lattice
ddr2
- ddr2的功能控制模块，3部分，只要调取就可以。-ddr2 control codes
ddr2_mem
- DDR2 xilinx ipcore 头文件 可以进行读写DDR2操作的接口! 读写时注意 按照时序控制进行！-DDR2 xilinx top file， you can read or write DDR2 interface。 attention：please control it ！
ug_ddr_ddr2_sdram_hp
- ALTERA DDR2高性能控制器使用文档，包括存储控制器、用户接口、用户测试模块，各控制信号的说明。-ALTERA DDR2 high performance controller using a document, including the memory controller, user interface, user testing module, the control signal descr iption.
DDR2Controller
- DDR2 SDRAM Control Verilog RTL Code
DDR2-verilog
- ddr2的Verilog代码，包括时序控制，数据读取，利用verilog编写的ddr2控制器，在spartan6板子上得以验证，成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the
DDR2_Control
- 本源码是用FPGA控制DDR2芯片的vhdl源码，并使用了modelsim仿真软件测试代码-The source is the use of FPGA control DDR2 chip vhdl source, and the use of modelsim simulation software test code
DDR2_Control
- 参考例程之Verilog之实现DDR2时序控制实现，ISE开发平台完整工程(Implementation of DDR2 timing control implementation of reference routine Verilog, complete engineering of ISE development platform)
DDR2_Control
- 本人用verilog编写的DDR2控制器，经测试可用。(I am prepared to use verilog DDR2 controller, the test is available.)