搜索资源列表
FIFO
- FIFO，命名管道。对linux命名管道的一些归纳，总结。希望对大家有帮助。你说好不好-FIFO, named pipe. Linux named pipe on a number of summary, in conclusion. We want to help. You say good
FIFO
- 先进先出算法 fifo 时自己编写的 有注释 很简单-Fifo FIFO algorithm when there are notes I have written is very simple
FIFO
- FIFO以及跨时钟域的同步问题。 FIFO有分离的地址总线和用以读写数据的数据通道，以及指示堆栈状态（满、将满等）的状态线。-FIFO as well as cross-clock domain synchronization. FIFO have separate address bus and read and write data to the data channel, as well as the instructions state stack (full, will be fu
fifo
- a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
Fifo
- Shows how to set up a FIFO data queue for sharing data between real-time tasks and user-level applications. The RT task creates two FIFOs, one for commands in from the user process and one for status back to the user process. As declared in
fifo
- 标准的先进先出队列数据结构,已经调试过的，可以直接应用到项目中-Standard FIFO queue data structure, has been testing, can be directly applied to projects
fifo
- 格雷码对地址编码的异步FIFO的实现方法-Gray code encoding to address the realization of the asynchronous FIFO method
FIFO-UART
- 基于ARM7-LM3S1138的FIFO方式的UART数据传输代码-ARM7-LM3S1138 based on the FIFO mode of UART data transmission code
FIFO
- 异步fifo,希望能给大家带来帮助-异步fifo
FIFO
- 完整的FIFO完整源代码，通过仿真 完整的FIFO完整源代码，通过仿真 -Complete FIFO full source code, through the simulation of the complete FIFO full source code, through the simulation of
fifo
- 同步FIFO 创建一个256x8大小的同步FIFO，并通过串口发送数据初始化FIFO，FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO
fifo
- 用FPGA做的fifo，源码，调试通过，有工程和波形文件-FPGA to do with the fifo, source code, debugging through, there are engineering and waveform file
fifo
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
fifo
- fifo使用手册，对于用IP core使用非常方便-fifo manual, for use with the IP core is very convenient
fifo
- 这个是我自己写的同步fifo ,供大家参考学习-this the syn-fifo,including testbench
FIFO.tar
- FIFO design VHDL/Verilog design
FIFO
- 先入先出FIFO，用QUARTUS进行仿真-FIFO FIFO, the simulation with QUARTUS
fifo
- 这是一个用VHDL编写FIFO模块，已经通过测试-fifo
syn-fifo-verilog
- 用verilog语言写的同步FIFO设计源代码。-The source codes for syn-fifo using verilog language.
FIFO
- FIFOFile name:FIFO //Describe:32*32bit FIFO //Input:data[31:0],wrreq,rdreq,clock //Output:q[31:0],full,empty //Date:2009-12-10 -FIFO