搜索资源列表
Xilinx_FPGA_tutorial
- Xilinx ISE软件使用实例 Foundation入门 参数编辑 设计管理器/设计流程向导 FPGA editor 底层编辑器(floorplanner) 硬件调试器（hardware debuger) JTAG编程（JTAG Programmer) LogiBLOX Xilinx FPGA设计进阶 FPGAexpress的使用 Vertex器件结构 层次设计和同步电路设计 HDL设
eetop.cn_licgen_ise_13.1
- this the license genarator for xilinx ISE DESIGN SUIT 13.1 -this is the license genarator for xilinx ISE DESIGN SUIT 13.1
LCD
- LCD1602的程序，只需改一改显示常量就可以！在ISE中调试成功-LCD1602 process, just simply show the constants can be! Successful commissioning of the ISE
61EDA_C2194
- < xilinx ise 9.x fpga cpld设计指南>>, xilinx设计经典中的经典书籍,讲得非常全面.是fpga设计人员不可或缺的书籍-xilinx design classic of the classic books, put it very comprehensive. fpga design is an indispensable book
ddc_FPGA
- 简要介绍了数字下变频的设计，通过采用xilinx的ise软件，ipcore的调用实现-Briefly introduced the design of digital down conversion, through the use of ise the xilinx software, ipcore call the realization of
ISim
- ISE仿真深度教程。讨论 ISE Simulator和Project Navigato-ISE Simulator(ISim) in-depth,introducing ISE Simulator和Project Navigato
VGADIY
- 自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
project_UHF_ddc
- vhdl语言写的数字下变频的实现，整个工程文件，xlinx ise用的-VHDL language written in the realization of digital down conversion, the whole project file, xlinx ise used
Chapter10
- 使用方法： 以太网编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: Ethernet programming, copied to the hard drive, open the project file with ISE can
ECCgenAndLoc
- 基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序，EccErrLoc文件夹为ECC错误定位程序。-Xilinx ISE environment based on the development of VHDL the NAND flash ECC to achieve, eccGen256Byte folder produced for the ECC procedures, EccErrLoc folder l
Xilinx_FPGA
- 介绍了FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE-Introduced the entire FPGA design process: Modelsim>> Synplify.Pro>> ISE
ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
traffic_controller
- it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code written for traffic light controlle
UART_for_FPGArar
- it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll
clock
- 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
D_BLAST44
- MIMO 4*4系统D-BLAST编译码方案，利用ISE仿真环境，verilog编程实现。-MIMO 4* 4 system codec D-BLAST program, using ISE simulation environment, verilog programming implementation.
Xilinx
- to generate keygen for xilinx family ise edk
uart_ise_vhdl
- fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file
mcu_8
- 使用函数实现简单的八位处理器 软件开发环境：ISE 7.1i 仿真环境：ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个可以进行两个八位操作数四种操作的简单处理器； 2. 工程在project文件夹中，双击mpc.ise文件打开工程； 3. 源文件在rtl文件夹中，mpc.v为设计文件，mpc_tb.tbw是仿真波形文件； 4. 打开工程后，在工程浏览器中选择mpc_tb.tbw，在Process View中双击“Si