搜索资源列表
FIFO
- 一个用VHDL源码编写的先进先出(FIFO)缓冲器模块.可以进行FIFO的仿真验证-A source prepared by VHDL FIFO (FIFO) buffer module. Can verify FIFO simulation
vhdlfi
- fifo vhdl源码，高可靠性，带有格雷码同步，有需要可依进行参考！-fifo vhdl source, high reliability, with Gray-code synchronization, there is a need-based reference!
PIC
- 一个PIC单片机内核的VHDL实现，包含VHDL源码，说明文档-A PIC Singlechip realize VHDL core, including the VHDL source code, documentation
ARM7_core
- ARM7内核,vhdl源码形式，不可多的的好东西。-ARM7 core, vhdl source code form, not the many good things.
jiaotongdeng
- 交通灯控制系统VHDL源码，用VHDL语言、MAXPLUS2环境设计实现-VHDL core
Mars_EP1C6F_Interface_demo(VHDL)
- FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。-FPGA development board support VHDL code. Chips for the Mars EP1C6F. Some of the source interface. Including 7 digital tube, I2C communications.
simple_fm_receiver.tar
- 一个简单FM接收机的VHDL源码，很有参考意义-A simple FM receiver VHDL source code is very useful
xapp345_vhdl
- adc转换功能的vhdl源码，其中包含adc_interface 和转换还包含串口输出-adc tranfer
tripledes
- 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
fsk
- 关于FSK调制的FPGA实现，有VHDL源码-FSK modulation on the FPGA, a VHDL source code
MAIN_RX_V10
- 8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.
cpld_ccd
- 实现基于CPLD的CCD采集系统设计的VHDL源码，编译通过，-Implementation of the CCD acquisition system based on CPLD design of VHDL source code, compiles,
VHDL-PCI
- PCI 源码 vhdl 非常好的东东 哈哈 -PCI vhdl very good ！ haha haha haha
PN_code_capture_and_tracing
- 一个完整的pn码捕获与跟踪的VHDL源码,并行匹配滤波器捕获,锁相环跟踪.-A complete pn Code Acquisition and Tracking of the VHDL source code, parallel matched filter to capture, phase-locked loop tracking.
IU3
- sun公司的sparc结构之整数处理器vhdl源码-The file is the RTL of the Sparc s integer unit.
JPEG2000
- 用于JPEG2000的53小波VHDL源码-53 for the JPEG2000 wavelet VHDL source code
fft(VHDL)
- 该源码是fft的VHDL实现，通过FPGA下载验证通过-The source is the fft of the VHDL implementation, through verification by FPGA download
TB_VHDL(adder)
- 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
PULSE
- 这是一个将6组并行数据串行输出的VHDL源码，配合外部电路可以输出正负脉冲，还附有逻辑图哦。-This is a group of parallel data to serial output 6 of the VHDL source code, with the external circuit can output positive and negative pulses, also with a logic diagram oh.