搜索资源列表
TMS320C6455
- tms320c6455 High-Performance Fixed-Point DSP TMS320C64x+™ DSP Core Enhanced VCP2 Enhanced Turbo Decoder Coprocessor (TCP2) 64-Bit External Memory Interface (EMIFA) Four 1x Serial RapidIO® Links (or One 4x), DDR2 Memory Controll
s3ask_ddr2
- DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
c_xapp454
- 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and t
c_xapp858
- 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the i
49636967xapp935
- DDR2驱动方面的资料,很有用的。希望对大家有用-drive of DDR2
LPC2DDR2
- Module Function Descr iption: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the
ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
AMBA
- 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
mcb_read_write
- 赛灵思 DDR2 用户接口程序 原创。希望对各位有用。-Xilinx DDR2 original user interface program. You want to be useful.
Xil3SD1800A_MIG
- 基于xc3sd1800afg676的开发板的DDR2的控制器的IPCORE，提供完整的代码和UCF。系统时钟频率为125Mhz。-The development board based on xc3sd1800afg676 DDR2 controller of IPCORE, provide a complete code and UCF. System clock frequency of 125Mhz.
DDR2PCBLayout
- TMS320DM643X系列DDR2的PCB布局-Implementing DDR2 PCB Layout on the TMS320DM643x
DDR SDRAM Design Tutorials
- Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
DDR2deFPGAsheji
- 使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器以及DDR2 SDRAM操作时序-Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing
the_design_and_realization_of_DDR2-SDRAM_controlle
- ddr2控制器的设计与实现,详细介绍了其结构和思想-the design and realization of DDR2-SDRAM controller
DDR2_controller
- DDR2控制器IP的设计与FPGA实现，使用verilog语言-DDR2 Controller IP Design and FPGA implementation, use the verilog language
mt48lc16m4a2
- DDR2 仿真模型 DDR2 仿真模型-DDR2 Simulation Model
ssss
- spartan—3a对ddr2读写控制源程序，有verilog和vhdl版本-spartan-3a ddr2 read and write control of the source, there are versions of verilog and vhdl
ddr2_test
- 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi