搜索资源列表
Altera-Lab-5
- Altera Lab 5 for DE1 - Manual and Solution
TAlttera_SSDh
- 使用的Altera的DE1 的板子进行SD卡上音乐的读取。 -The use of Altera' s DE1 board to read music on the SD card.
nguyenvanduan_group4_TC304
- ASM chart for altera de1
audio
- 基于DE1开发板，实现录音和播放功能，并可将存入sram中的语言数据通过uart传回电脑。-Based on DE1 development board, recording and playback functions, and can be stored in sram language data back to the computer via uart.
DE1lab1
- DE1 altera VHDL lab 1 exercise
DE1lab2
- DE1 lab2 altera Vhdl
as1
- Verilong HDL是最frequenctly使用的硬件描述语言，因为它的简单和方便的属性之一。这当然AIMES设计一个数字时钟，配备4段显示，秒表和时间设定使用这种语言，甚至一些额外的功能，fundamatal。 DE1板设计时钟的实施贡献-Verilong HDL is one of the most frequenctly used hardware descr iption language because of its simple and convenient propertie
DE1_synthesizer
- DE1 music synthesizer
FREQ-DIV-50MHz-to-64kHz
- Frequency divider implement on DE1 board, Clock in (OSC = 50MHz)to 64kHz
de1_camera_demo
- DE1 Demo Quartus Project (A Study of Spatial Color Interpolation Algorithms)
audio_latest.tar
- Audio Codec(ADPCM 1-Bit) The code is ready for Altera Cyclone-II DE1 Starter board and it is tested, you can modify codes and use them in any project. Core Descr iption: Sampling Frequency: 44100Hz Channels: Stereo Bit-rate: 1 Bit Per Sa
DongHo
- design a clock using KIT DE1
Pong
- ping pong game fpga DE1
vga-example
- Basic VGA implementation on the Altera DE1
stopwatch9_02-_2---worked
- 一个基于DE1开发板制作的秒表，拥有启动，暂停，停止功能 内置寄存器，可以在计时是存储显示当前时间-DE1 development board based on the production of a stopwatch with start, pause, stop, features built-in registers that can be stored in the timing display the current time
audio1
- a good vhdl code for audio configuration altera de1 bored a good vhdl code for audio configuration altera de1 bored a good vhdl code for audio configuration altera de1 bored -a good vhdl code for audio configuration altera de1 bored a good vhdl code
First_test_Blinking_LEDs
- my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds -my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds my first
DE1_Default
- this the default setting for DE1 board that will reprogram the board to the default setting-this is the default setting for DE1 board that will reprogram the board to the default setting
DE1_SoC_i2sound
- FPGA控制麦克风播放语音程序,在DE1-soc开发板上面实现-FPGA control microphone to play the voice program, DE1-soc development board to achieve the above
Altera_Audio
- 针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。-The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.