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divider-achieved-by-verilog
- 该代码用Verilog语言实现了分频功能，主要实现对输入时钟的54分频，已通过仿真验证。-The code in Verilog realize the crossover functions, the main achievement of the input clock frequency of 54 minutes, has been verified by simulation.
frequency-generation
- 基于VHDL语言的分频器，输入四位比特控制产生相应的输出频率。-Frequency divider based on VHDL language, input control four bits to produce the corresponding output frequency.
divider
- FPGA 循环拼接除法 循环拼接除法-FPGA Loop stitching DivisionLoop stitching Division
8-bit-Restoring-Divider
- Division is performed in four stages. After reset, the 8-bit numerator is “loaded” in the remainder register, the 6-bit denominator is loaded and aligned (by 2N− 1 for a N bit numerator), and the quotient register is set to zero. In the second a
ViewSpliter
- 进行窗口的自动分割，并能自动设置分隔条的位置和分割窗口的大小。-Automatic segmentation of window, and can automatically set the size and location of the divider partition window.
4.5fenpingqi
- 基于FPGA的关于verilog语言的4.5分频器及其仿真波形图-FPGA based on verilog language frequency divider and its simulation waveform in figure 4.5
fenpinqi
- 数字分频器，包括分频器单位冲击响应及幅频响应-Digital frequency divider, including frequency divider unit impulse response and amplitude frequency response
adc12
- 基于msp430f149两路ad采样，并由lcd显示，采样可有电阻分压扩大显示范围。-Based msp430f149 two ad sampled by lcd display, sampling resistor divider may have to expand the display range.
pulse8
- 任意占空比的8分频电路,也可以任意分频，经过优化，很稳定-Arbitrary duty 8 divider circuit may be arbitrarily divided optimized, very stable
fdivision
- 在quartus平台下，并使用verillog hdl编写的时钟分频仿真-In quartus platform and use verillog hdl write clock divider simulation
N-jifenpin
- 用verilog编写的N倍奇分频源码，大家可以参考一下哈哈哈。希望大神指正-With verilog written N times odd divider source code, you can refer to Ha ha ha. Great God hope corrected
DIV
- 最新修改 veilog 除法器，32位除16位，输出数据锁存-//divider dividend divisor* quotient+ remainder //dividend 32 bit //divisor 16 bit //quotient 32 bit //remainder 32 bit //need 32 clk to finish the calculation //start 1 start the calculation //s
7-BCD
- 7段数码管控制接口程序和对初始频率为50MHZ的时钟的分频程序-7-segment control interface program and the initial frequency of 50MHZ clock divider program
7771_reg-voltage_ApplicationNote
- There are variety ways of building 3.3V power supply, such as using voltage divider, voltage regulator and DC-DC converter.
AC220V-DC4.2V
- 本设计设计手机充电器系统，实现由交流220V电能到直流4.2V电能的转换，进而为手机等设备充电。在系统控制中采用了变压、整流、滤波、稳压、分压、电压检测等电路，并且具有一定的充电提示和充满电自动断电的功能。 本设计采用Proteus（V7.1）软件仿真进行演示。-Based on Proteus simulation design phone charger system, implemented by 220V AC power to DC 4.2V power conversion. I
UD_DIVDER
- 定制化分频器的verilog源代码，分频器变量已参数化，好用-Customized divider verilog source code, variable frequency divider parameterized, easy to use
half_integer
- 数控分频器：以2.5分频为例的半整数分频器-half-integer frequency divider
div84
- An 8-Bit Divider using a Procedure
traffic-light
- （1） Divid 模块：1Hz 分频模块，开发板提供50MHz 的系统时钟，而该设计交通灯 转换以秒为计时单位，对50MHz 分频得到1Hz 脉冲信号。 （2） Divid_200 模块: 200Hz 分频模块,用于产生动态扫描模块的时钟。一个数码管 稳定显示要求的切换频率要大于50Hz，那么4 个数码管则需要50×4＝200Hz 以上 的切换频率才能看到不闪烁并且持续稳定显示的字符，因而扫描频率设定为 200Hz。 （3） Control 模块：A、B 方向红绿灯控制
resistance_calculator
- 硬件设置小工具，电阻值计算excel，表列出了常用电阻值，只需要输入电源电压，需要电压俩个电压值，就可以算出分压电阻，误差5 以内会有绿色标注-Hardware settings gadgets, resistance calculation excel, table lists the commonly used resistance, only need to input power supply voltage, the need to voltage two voltage values