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devider
- a divider design based on verilog language
dividers
- verilog格式的除法器，试过了，很好用，再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
Divider
- 一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl
restoring
- restoring除法器设计 经典算法了，可以仿真通过-divider restoring a classical algorithm design, simulation can be adopted
divide
- It is n-bit sequential divider in verilog language
juzhenqufaqi
- 基于FPGA单精度浮点除法器的实现，有一些源代码，仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
chufaqichengxu
- 除法器程序，除法器模块，定点数除法的相关代码。-Divider procedures, divider module, the related fixed-point code division.
clock_divider
- This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock.
ref
- non-storing divider in verilog code
HG_chufaqi_clajiafaqi
- VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
f_divider
- 16-bit frequency divider (32 MHz,16,8,...) based on altera fpga.
divider
- 几个有用的分频器电路的VHDL实现。有需要的进来-The divider using VHDL code. if you want, please come in. welcome to give some suggestion. Thank you.
Freq_Divider
- frequency divider using verilog
Divider-design-in-three-ways
- 三种方式设计的分频器（常用于产生秒脉冲）-Divider design in three ways (often used to produce second pulse)
divider_latest.tar
- floating point divider
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
divider
- divider code .. in VHDL language
5956447divider
- 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the
divider
- 流水型除法器，经过FPGA平台验证。宽度可以任意修改，提供计算完毕信号。-Water-type divider, after a FPGA platform validation. Width can be modified to provide the calculation is completed the signal.