搜索资源列表
16_16DIV
- 多位数除法程序，满足在单片机编程中对除法程序的需要，解决了单片机指令无除法程序的缺点，而且本程序不限制位数。-over the median divider, which meets in MCU Programming division procedures to the needs of SCM solutions division procedures directive without shortcomings, but the procedure does not limit the
8-bit-ALU-with-a-Newton-Raphson-Divider
- 8-bit ALU with a Newton-Raphson Divider Using Verilog
DIVIDER
- M进制计数器 verilog code for divider-verilog code for divider verilog code for dividerverilog code for divider
divider
- 主要是基于VHDL的五位除法器设计，基于eda试验箱的设计。-Five main divider VHDL-based design, based eda chamber design.
float-point-divider
- 基于FPGA的单精度浮点除法器vhdl设计程序,分模块程序。-FPGA-based single-precision floating point divider vhdl design program, sub module program.
DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
Design-of-divider
- 除法器设计在FPGA板上的应用 除法器设计在FPGA板上的应用-The application of FPGA in design of divider class.
greatest-common-divider
- 一个用于计算两个数的最大公约数的逻辑算术单元-an arithmetic logic unit which is used to calculate the greatest common divider of two numbers
divider
- 用Verilog实现的除法器，通过了编译和测试，可以放心使用。-Divider implemented using Verilog, by compiling and testing, you can rest assured that use.
divider
- 输出任意频率的分频器，使用verilog语言实现-The divider wright using verilog
divider
- 分频器。可实现任意整数分频。占空比为50％，带复位端。-Frequency divider Arbitrary integer frequency can be achieved. Duty cycle is 50 , with reset terminal.
Frequency-divider
- 利用Verilog设计的在停车场情况下的模拟的分频器和计数器的代码-The use of Verilog design in the parking lot in case of analog frequency divider and counter code
NC-divider-design
- 1、 学习数控分频器的设计、分析和测试方法。 2、 了解和掌握分频电路实现的方法。 3、 掌握EDA技术的层次化设计方法。 -NC divider design
design-of-divider-
- 应用FPGA软件编写的关于除法器的小程序，适合初学者学习，很实用，而且很简单，-FPGA application software prepared by the divider small program for beginners to learn, very practical and very simple, Ha ha ha
divider
- a vhdl code for divide operation in fpga spartan6
7P(divisionymulti)
- divider and multiplier number labview
Divider
- 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)
Divider
- this is divider for verilog
frequency divider and testbench
- a frequency divider and test bench with simulation results
RPWM-matlab
- clock divider program by using VHDL