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pipeline
- 某石油公司计划建造一条由东向西的主输油管道。该管道要穿过一个有n 口油井的油田。从每口油井都要有一条输油管道沿最短路经(或南或北)与主管道相连。如果给定n口油井的位置,即它们的x 坐标(东西向)和y 坐标(南北向),应如何确定主管道的最优位置,即使各油井到主管道之间的输油管道长度总和最小的位置?证明可在线性时间内确定主管道的最优位置。 给定n 口油井的位置,编程计算各油井到主管道之间的输油管道最小长度总和。-Oil pipeline Problem iadhf djsfhl sdhnfkj sl
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码,在ModelSim中仿真通过,并且在ISE中能综合!即可以下载到FPGA中运行指令,指令可以根据需要定义,也可和相应的编译器配合使用,这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
waterline_adder.rar
- 这是一个用Verilog编写的四级流水线加法器,This is a Verilog prepared with four pipeline adder
FIFO_8_8
- FIFO先进先出队列,一种缓存、或一种管道、设备、接口(Verilog HDL程序,内附说明)-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境,使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令(均不考虑虚拟地址和Cache,并且默认为小端方式): add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
Pipeline
- java写的关于流水线工作过程的模拟程序-java to write the work on the assembly line process simulation program
mips
- 在maxplus上实现了一个5级流水线的mips cpu,含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
Pipeline
- 高级计算机体系结构实验, 非线性流水线调度-none-linear pipeline
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
bp
- 本书涉及的研究方法主要应用于油田生产的实际工作中,包括一般储层参数预测、薄互油藏参数预测、火山岩储层参数预测和储层随机模拟等问题,同时还涉及了石油工业中的油管缺损检测、海底输油管道腐蚀检测等应用问题,对污水处理絮凝过程的智能优化控制及移动机器人的全局和局部路径规划等问题的应用也进行了一定的研究。-Book of research methods involved are mainly used in oil field production of practical work, includi
MIPS
- mips处理器指令仿真器,可查看流水线执行方式-mips instruction processor emulator, you can review the pipeline implementation
Pipeline_FFT
- Descr iption of a pipeline architecture for a FFT processor, based on the R22SDF algorithm.
GPUGems1
- GPU Gems is a compilation of articles covering practical real-time graphics techniques arising from the research and practice of cutting-edge developers. It focuses on the programmable graphics pipeline available in todays graphics processing units (
MIPS
- 带分支预测的MIPS流水线的verilog原代码。 详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
Pipeline
- 计算各油井到主管道之间的输油管道最小长度总和。-Pipeline
CPU_verilog
- 一个4级流水线CPU的verilog代码,供参考学习使用,有些语句不能综合,可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
pipe
- This an example of pipeline implemented in SystemC-This is an example of pipeline implemented in SystemC
Fire
- firestarter – A Real-Time Fire Simulator Many obstacles exist in attempting to graphically render physical phenomena that are highly fluid and ostensibly chaotic in nature. Fire is a prime example of such phenomena. Given the unrealizable compu
cordic
- vhdl语言编写的cordic算法,实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.