搜索资源列表
flowmeter-pipeline-system
- 基于电磁流量计的管道流量检测系统，很不错适用的一个完整的程序。-Based on the the electromagnetic flowmeter pipeline flow detection system, very good applies to a complete program.
Pipeline-2.zip
- Pipeline processor verilog components ,Pipeline processor verilog components
Pipeline-and-FIFO
- Pipeline and FIFO的FPGA设计-Pipeline and FIFO FPGA design
8-grade-4-pipeline-adder-Verilog
- 这是一个8位4级流水线的加法器的Verilog程序。-This is a eight grade 4 pipeline adder the Verilog program.
OpenGL-pipeline-and-coordinate
- OpenGL图形管线和坐标变换，讲解得很清晰易懂-OpenGL graphics pipeline and coordinate transformation, to explain the very clear and easy to understand
Pipeline
- 石油工业中长输管道经济性分析 包括运行费用和建设费用 采用敏感性分析-Economic Analysis of the oil industry in the long-distance pipeline, including operating costs and construction costs using sensitivity analysis
pipeline
- 一个流水线设计提高FPGA运行主频的实例-a pipeline demo for FPGA written with verilog
Pipeline
- 接水管智力小游戏，有游戏功能和自动实现接水管功能。-This is an interesting pipeline-stitching game. It is not only a game for fun but also can perform pipeline-stitching automatically.
Gas-pipeline-construction
- 本方案详细叙述了城市燃气管线管理系统的详细建设思想和方法，可以用于系统的开发。-A detailed descr iption of the program management of city gas pipeline system for the detailed construction of ideas and methods can be used for system development.
Structural-Pipeline-Multiplier
- Structural Pipeline Multiplier
pipeline-relocation
- 使用MFC运行外部程序，并获取输出显示在编辑框，比如运行bat，并把bat所有的输出输出到编辑框。 主要使用管道重定位等相关技术。-Run an external program using MFC, and get the output displayed in the edit box, such as running a bat, and the bat all the output to edit box. Mainly used pipeline relocation and othe
DLX-pipeline-in-verilog
- verilog实现DLX指令集5段流水线-5 stage DLX pipeline implemented in verilog
Report RISC in Verilog
- Report RISC in Verilog.16-bit. 5-stage pipeline
pipeline
- 实现LINUX 经典流水线算法。 PIPELINE，即将各个工作阶段插入链表，下一个的输入，依赖于上一个的输出-Achieve LINUX classic lines algorithms. PIPELINE, each session is about to insert the list, the next input, the output depends on the previous one
Pipeline
- Windows下，匿名管道通信 VC6环境-pipeline communicate
pipeline
- 使用VERILOG實現MIPS2000的PIPELINE-Use VERILOG realized MIPS2000 the PIPELINE
MIPS Pipeline
- A program to simluate the MIPS pipeline
PipeLine-GCD-DSP
- 流水线结构的最大公约数处理器，处理的数据为32bit,采用64级流水线实现。-A pipeline sturcture GCD DAC, data width is 32bit.
Pipeline
- 用图形界面演示模型机的指令序列在5级流水线上的执行过程。使用高级语言Java，在Eclipse环境下开发流水线的仿真程序。实现针对任意的无相关模型机指令序列（包括数据前推、load前推并解决控制相关），能单步显示出每个时钟周期流水线上指令的执行情况，具体包括：时钟周期及编号、各级流水线寄存器的内容、各级流水线的控制信号。- Graphical interface demo model machine instruction sequence is d on five pipeline. U
Water-Pipeline-Project-P-Comparison
- Water Pipeline Full Excel Design with Comparison with Oil