搜索资源列表
USB
- USB源代码，基于VHDL语言编写，在QuartusII上面已验证其功能-USB source code, based on the VHDL language, verified in QuartusII above its function
dianji
- QuartusII环境下，用于upds实验板的三相六拍电机-QuartusII environment, for the three-phase experimental board upds shot six motor
dds
- 这是一个用vhdl语言实现dds的例子，已在quartusII里调通并可以下载到实验箱上，功能正确-This is a use of VHDL language dds example, has been in tune quartusII pass and can be downloaded to the experimental box, the function correctly
HowtousemodelsiminQUartusII
- 如何在QuartusII中使用Modelsim的使用文档，方便仿真-How to use ModelSim QuartusII the use of documents to facilitate the simulation
quartus2
- 主要是关于FPGA的开发软件QUARTUSII的学习文档和一些常用操作方法工具等-Mainly on the development of FPGA software QUARTUSII study documents and method of operation of some commonly used tools, etc.
2-QUARTUSII
- 让大家更加的了解EDA技术在日常生活中的重要性。-Let us be more understanding of EDA technology in daily life importance.
vga_colors
- 该项目在VGA显示器上显示8色竖彩条。使用VerilogHDL语言编写，在Altera公司的QuartusII开发环境下验证通过。-The project was displayed on the monitor VGA color vertical color 8. VerilogHDL language used in Altera' s development environment QuartusII verification through.
vga_line
- 该项目在VGA显示器上显示一条从屏幕左上角开始，呈135度角的水平线。使用VerilogHDL语言编写，在Altera公司的QuartusII开发环境下验证通过。-The project was displayed on a VGA monitor from the top left corner of the screen to start, showing 135-degree angle of the horizon. VerilogHDL language used in Altera&
lcd1602-verilog
- 基于QuartusII的LCD1602-Verilog 源代码，可以直接应用于FPGA开发板。-QuartusII based on the LCD1602-Verilog source code, can be directly applied to FPGA development board.
QuartusII
- 在quartus2中实现过的VHDL源码。已经试用过。-Medium quartus2 at implementation of the VHDL source code too. Have tried them already.
lcd_demo
- 一种基于FPGA和quartusII技术开发的彩色LED显示测试程序-colored LED
lcdfinal
- LCD显示，用verilog写的，quartus-LCD display，verilog，quartusII
fir_compiler-v3.3.1
- ALTERA公司的quartusII fir_compilier-v3.31对工程师很有帮助的哦-ALTERA company quartusII fir_compilier-v3.31 helpful for Engineer
VHDL
- 实现一个10秒倒计时电路，要求使用8*8点阵显示计时结果。在QuartusII平台上设计程序和仿真题目要求，并下载到实验板验证实验结果。-Achieve a 10-second countdown circuit, requires the use of 8* 8 dot matrix display timing results. QuartusII platform in the design process and simulation on the subject request and
FIFO
- 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
rei2c
- 用VHDL编写的quartusii平台上的串行EEPROM配置读取的程序。-Quartusii prepared using VHDL platform to read the serial EEPROM configuration procedures.
golomb
- golomb编码，用于无损图像压缩等，基于quartusii平台。-golomb coding for lossless image compression, based on the platform quartusii.
16qam——modulation
- verilog编写的16qam调制程序，将所有东西装入工程，运行mmm16主程序。其中载波为一个周期采十个点，并乘以2^8-1取整数。在quartusII运行通过。-verilog modulation procedures 16qam prepared all things into works mmm16 to run the main program. One carrier for a cycle of 10 points taken, and multiplied by an inte