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rs232
- 基于QuartusII的RS232的串口编程实验，包括有波特率的改变-Based on the RS232 serial port programming QuartusII experiments, including the baud rate change
test_ad9852
- 使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。-Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.
Nios_II_timer
- 本源码为Nios II的开发示例,主要演示Nios II的定时中断器的应用。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusI
zigbee_sensor
- ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信） -ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear qua
FPGA_NES_Version_1.0
- 用ＦＰＧＡ制作的ＮＥＳ游戏主机（８０后都知道的游戏主机）的ＶＨＤＬ代码，在ＱｕａｒｔｕｓＩＩ下编译通过。有兴趣的朋友一起交流。-FPGA produced with NES game console (80 after all know the game host) of the VHDL code, compiled under the QuartusII through. Are interested in sharing with friends.
EDA-elevator-controller
- 在QuartusII里用VHDL仿真实现电梯控制器-QuartusII elevator controller VHDL Simulation
Modelsim6.4a-Crack_QII90
- Modelsim-ALTERA 6.4a （配合QuartusII 9.0) crack详细说明 Modelsim-ALTERA 6.4a的详细破解说明，步骤有点麻烦哦，仔细按PDF里说明的做就OK了-Modelsim-ALTERA 6.4a detailed descr iption of steps to break, a little trouble Oh, carefully press the PDF illustrated do OK
eda
- 这是一个基于quartusII软件编写的程序，可以进行电梯控制。-This is written based on quartusII software program can be elevator control.
wavegenerator
- 开发环境为QuartusII，能产生正弦波、三角波、方波和锯齿波，幅度为5V，采样为8位，在开发板已经验证通过，有详细的波形图和管脚分配图。-Development environment for QuartusII, can generate sine wave, triangle wave, square wave and sawtooth wave, ranging from 5V, sampling for 8, in the development board has to verif
recuart_50m
- 本代码功能为实现接收PC发送的串口数据功能 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions to achieve the receivi
dds
- verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件，-verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
FPGA_COM
- FPGA实现的多串口程序(支持收发中断，QUARTUSII编译),各串口独立-FPGA serial program (support to send and receive interrupt, QUARTUSII compiler), the serial independence...
autoConter
- 基于quartusII的自动售票机电路图-Based on the vending machine circuit quartusII
hanming
- 产生m序列作为输入信号，能够实现(7,4)汉明码编码和译码功能。同时，还有加噪模块。 在QuartusII工作环境下使用-M sequence generated as the input signal, can be achieved (7,4) hamming code encoding and decoding functions. There are also additional noise modules. Working environments in the QuartusI
pcirw
- quartusII环境下实现FPGA与PCI9054通信。根据PCI9054规范控制lhold、lholda、ads、blast、lbe、lwr等握手信号的时序，可完成上位机通过PCI总线读写FPGA本地地址空间的功能- Communication between FPGA and PCI9054 in QuartusII IDE.Implementation for the timing of handshake signals such as lhold, lholda, ads,bla
MIPS
- MIPS处理器的组员大作业，可以直接运行，提交，环境是quartus-MIPS processor crew great job, you can run directly, the author, the environment is quartusII
second7-02
- 在quartusII环境下采用对编解码芯片HD6408和HD6409驱动的方式实现曼彻斯特编解码-Environment in quartusII codec chip used on the HD6408 and HD6409-driven way to achieve encoding and decoding of Manchester
Electronic-Clock_1.11
- 用quartusii 设计的电子钟原型文件-Electronic clock with quartusii prototype file design
digi_clock2.7z
- 數位電子時鐘 用自製圖檔製成 不是用quartusII 內建的圖檔製成 -Digital electronic clock with self-image made of instead of the built-in image quartusII made